Patents by Inventor Dai-Guo Xu

Dai-Guo Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10666243
    Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 26, 2020
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Dai-Guo Xu, Gang-Yi Hu, Ru-Zhang Li, Jian-An Wang, Guang-Bing Chen, Yu-Xin Wang, Dong-Bing Fu, Tao Liu
  • Publication number: 20190334514
    Abstract: A high-speed low-power-consumption dynamic comparator includes a latch, an AND gate, a delay unit, and an XNOR gate. According to the high-speed low-power-consumption dynamic comparator, the output signal is generated through the XNOR gate from the comparator output signals Dp and Dn. The output signal and the control signal clk1 generate the control signal of the NMOS transistor P10 through the AND gate, so that the problem of static power consumption in a conventional comparator is solved.
    Type: Application
    Filed: July 7, 2016
    Publication date: October 31, 2019
    Inventors: DAI-GUO XU, GANG-YI HU, RU-ZHANG LI, JIAN-AN WANG, GUANG-BING CHEN, YU-XIN WANG, DONG-BING FU, TAO LIU
  • Patent number: 9966967
    Abstract: A high-speed successive approximation analog-to-digital converter of two bits per cycle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: May 8, 2018
    Assignee: CHINA ELECTRONIC TECHNOLOGY CORPORATION, 24TH RESEARCH INSTITUTE
    Inventors: Dai-Guo Xu, Shi-Liu Xu, Gang-Yi Hu, Guang-Bing Chen, Jian-An Wang
  • Publication number: 20170331486
    Abstract: The present invention pertains to a high-speed successive approximation analog-to-digital converter of two bits per circle, includes three switches, two capacitor arrays, three comparators, an encoding circuit, a first switch array corresponding to the first capacitor array, a second switch array corresponding to the second capacitor array, a shifting register and a digital correction unit. The analog-to-digital converter, featuring doubled speed, realizes a successive approximation process without any fault when a high-bit large capacitor is unsettled. Thus no redundancy bit capacitor is required to compensate for unsettled pre-stage large capacitor. By using the encoding circuit, a thermometer code is converted into a binary code effectively, and inherent errors of comparators are reduced by the randomization of three comparators.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 16, 2017
    Inventors: Dai-Guo Xu, Shi-Liu Xu, Gang-Yi Hu, Guang-Bing Chen, Jian-An Wang