Patents by Inventor Daisuke Matsubayashi

Daisuke Matsubayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220059409
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Toshihiko TAKEUCHI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Daisuke MATSUBAYASHI, Noritaka ISHIHARA, Yusuke NONAKA
  • Patent number: 11257722
    Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: February 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuki Tanemura, Etsuko Kamata, Hiromi Sawai, Daisuke Matsubayashi
  • Publication number: 20220037373
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Application
    Filed: October 13, 2021
    Publication date: February 3, 2022
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Keisuke MURAYAMA
  • Publication number: 20220013529
    Abstract: A storage device of an embodiment includes a first conductive layer; a second conductive layer; a fluid layer between the first conductive layer and the second conductive layer; particles in the fluid layer; a first control electrode between the first conductive layer and the second conductive layer; a first insulating layer between the first conductive layer and the first control electrode surrounding the fluid layer; and a second insulating layer between the first control electrode and the second conductive layer surrounding the fluid layer. In this storage device, a first cross-sectional area of the fluid layer in a first cross-section perpendicular to a first direction is smaller than a second cross-sectional area of the fluid layer in a second cross-section perpendicular to the first direction. The first cross-section includes the first control electrode, and the second cross-section includes the second insulating layer.
    Type: Application
    Filed: March 11, 2021
    Publication date: January 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Daisuke MATSUBAYASHI, Masumi SAITOH
  • Patent number: 11217668
    Abstract: A miniaturized transistor with reduced parasitic capacitance and highly stable electrical characteristics is provided. High performance and high reliability of a semiconductor device including the transistor is achieved. A first conductor is formed over a substrate, a first insulator is formed over the first conductor, a layer that retains fixed charges is formed over the first insulator, a second insulator is formed over the layer that retains fixed charges, and a transistor is formed over the second insulator. Threshold voltage Vth is controlled by appropriate adjustment of the thicknesses of the first insulator, the second insulator, and the layer that retains fixed charges.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Kazuki Tanemura, Daisuke Matsubayashi
  • Patent number: 11195758
    Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: December 7, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshihiko Takeuchi, Tsutomu Murakawa, Hiroki Komagata, Daisuke Matsubayashi, Noritaka Ishihara, Yusuke Nonaka
  • Patent number: 11164871
    Abstract: A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takanori Matsuzaki, Yoshinobu Asami, Daisuke Matsubayashi, Tatsuya Onuki
  • Publication number: 20210328074
    Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Yoshiyuki KOBAYASHI, Daisuke MATSUBAYASHI
  • Patent number: 11152494
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 19, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Publication number: 20210320212
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Tetsuhiro TANAKA, Hirokazu WATANABE, Yuhei SATO, Yasumasa YAMANE, Daisuke MATSUBAYASHI
  • Publication number: 20210280718
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device in which first to third conductors are placed over a first oxide; first and second oxide insulators are placed respectively over the second and third conductors; a second oxide is placed in contact with a side surface of the first oxide insulator, a side surface of the second oxide insulator, and a top surface of the first oxide; a first insulator is placed between the first conductor and the second oxide; and the first oxide insulator and the second oxide insulator are not in contact with the first to third conductors, the first insulator, and the first oxide.
    Type: Application
    Filed: July 16, 2019
    Publication date: September 9, 2021
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke MATSUBAYASHI, Yuichi YANAGISAWA, Masahiro TAKAHASHI
  • Patent number: 11101386
    Abstract: A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor over the oxide; a third conductor over the oxide; a first insulator provided between the oxide and the third conductor and covering a side surface of the third conductor; a second insulator over the third conductor and the first insulator; a third insulator positioned over the first conductor and at a side surface of the second insulator; a fourth insulator positioned over the second conductor and at a side surface of the second insulator; a fourth conductor being in contact with a top surface and a side surface of the third insulator and electrically connected to the first conductor; and a fifth conductor being in contact with a top surface and a side surface of the fourth insulator and electrically connected to the second conductor.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 24, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryota Hodo, Daigo Ito, Hiroaki Honda, Satoru Okamoto
  • Patent number: 11088286
    Abstract: A semiconductor device with excellent electric characteristics is provided. The semiconductor device includes an oxide in a channel formation region. The semiconductor device includes the oxide over a substrate, a first insulator over the oxide, a second insulator over the first insulator, a third insulator, and a conductor over the third insulator. The oxide and the first insulator are in contact with each other in a region. An opening exposing the oxide is provided in the first insulator and the second insulator. The third insulator is placed to cover an inner wall and a bottom surface of the opening. The conductor is placed to fill the opening. The conductor has a region overlapping with the oxide with the third insulator between the conductor and the oxide. The first insulator contains an element other than a main component of the oxide.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 10, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota Hodo, Daisuke Matsubayashi, Motomu Kurata, Ryunosuke Honda
  • Publication number: 20210234025
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Application
    Filed: April 12, 2021
    Publication date: July 29, 2021
    Inventors: Junichi KOEZUKA, Yukinori SHIMA, Hajime TOKUNAGA, Toshinari SASAKI, Keisuke MURAYAMA, Daisuke MATSUBAYASHI
  • Patent number: 11056491
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a transistor, an interlayer film, and a first conductor. The transistor includes an oxide over a first insulator; a second conductor over the oxide; a second insulator provided between the oxide and the second conductor and in contact with a side surface of the second conductor; and a third insulator provided for the side surface of the second conductor with the second insulator therebetween. The oxide includes a first region, a second region, and a third region. The first region overlaps with the second conductor. The second region is provided between the first region and the third region. The third region has a lower resistance than the second region. The second region has a lower resistance than the first region. The interlayer film is provided over the first insulator and the oxide. The first conductor is electrically connected to the third region.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 6, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Tatsuya Onuki
  • Patent number: 11049974
    Abstract: A semiconductor device having a reduced amount of oxygen vacancy in a channel formation region of an oxide semiconductor is provided. Further, a semiconductor device which includes an oxide semiconductor and has improved electric characteristics is provided. Furthermore, a methods for manufacturing the semiconductor device is provided. An oxide semiconductor film is formed; a conductive film is formed over the oxide semiconductor film at the same time as forming a low-resistance region between the oxide semiconductor film and the conductive film; the conductive film is processed to form a source electrode and a drain electrode; and oxygen is added to the low-resistance region between the source electrode and the drain electrode, so that a channel formation region having a higher resistance than the low-resistance region is formed and a first low-resistance region and a second low-resistance region between which the channel formation region is positioned are formed.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 29, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe, Yuhei Sato, Yasumasa Yamane, Daisuke Matsubayashi
  • Patent number: 11031403
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 8, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Kiyoshi Kato, Katsuaki Tochibayashi, Shuhei Nagatsuka
  • Publication number: 20210090961
    Abstract: A semiconductor device with a high threshold voltage is provided. A first conductor positioned over a substrate, a first insulator positioned over the first conductor, a first oxide positioned in contact with the top surface of the first insulator, a second insulator positioned in contact with the top surface of the first oxide, a second oxide positioned over the second insulator, a third insulator positioned over the second oxide, and a second conductor positioned over the third insulator are included. A mixed layer is formed between the first insulator and the first oxide. The mixed layer contains at least one of atoms contained in the first insulator and at least one of atoms contained in the first oxide. The mixed layer has fixed negative charge.
    Type: Application
    Filed: July 18, 2018
    Publication date: March 25, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuki TANEMURA, Etsuko KAMATA, Hiromi SAWAI, Daisuke MATSUBAYASHI
  • Publication number: 20210036159
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Application
    Filed: October 8, 2020
    Publication date: February 4, 2021
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Keisuke MURAYAMA
  • Patent number: 10872981
    Abstract: A transistor includes oxide semiconductor stacked layers between a first gate electrode layer and a second gate electrode layer through an insulating layer interposed between the first gate electrode layer and the oxide semiconductor stacked layers and an insulating layer interposed between the second gate electrode layer and the oxide semiconductor stacked layers. The thickness of a channel formation region is smaller than the other regions in the oxide semiconductor stacked layers. Further in this transistor, one of the gate electrode layers is provided as what is called a back gate for controlling the threshold voltage. Controlling the potential applied to the back gate enables control of the threshold voltage of the transistor, which makes it easy to maintain the normally-off characteristics of the transistor.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 22, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Keisuke Murayama