Patents by Inventor Daisuke Matsubayashi

Daisuke Matsubayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899420
    Abstract: In a pixel including a selection transistor, a driver transistor, and a light-emitting element, as the driver transistor, a transistor is used in which a channel is formed in an oxide semiconductor film and its channel length is 0.5 ?m or greater and 4.5 ?m or less. The driver transistor includes a first gate electrode over an oxide semiconductor film and a second gate electrode below the oxide semiconductor film. The first gate electrode and the second gate electrode are electrically connected to each other and overlap with the oxide semiconductor film. Furthermore, in the selection transistor of a pixel, which does not need to have field-effect mobility as high as that of the driver transistor, a channel length is made longer than at least the channel length of the driver transistor.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Seiko Inoue, Shinpei Matsuda, Daisuke Matsubayashi, Masahiko Hayakawa
  • Publication number: 20180033807
    Abstract: A highly reliable semiconductor device capable of retaining data for a long period is provided. The transistor includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide and a second oxide over the first gate insulator, a first conductor over the first oxide, a second conductor over the second oxide, a third oxide covering the first gate insulator, the first oxide, the first conductor, the second oxide, and the second conductor, a second gate insulator over the third oxide, and a second gate electrode over the second gate insulator. An end portion of the second gate electrode is positioned between an end portion of the first conductor and an end portion of the second conductor in a channel length direction.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Inventors: Shinpei MATSUDA, Daigo ITO, Daisuke MATSUBAYASHI, Yasutaka SUZUKI, Etsuko KAMATA, Yutaka SHIONOIRI, Shuhei NAGATSUKA
  • Patent number: 9882058
    Abstract: A semiconductor device in which variation in electrical characteristics between transistors is reduced is provided. A transistor where a channel is formed in an oxide semiconductor layer is included, and a concentration of carriers contained in a region where the channel is formed in the oxide semiconductor layer is lower than or equal to 1×1015/cm3, preferably lower than or equal to 1×1013/cm3, more preferably lower than or equal to 1×1011/cm3, whereby an energy barrier height which electrons flowing between a source and a drain should go over converges at a constant value. In this manner, a semiconductor device in which variation in the electrical characteristics between the transistors is inhibited is provided.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 30, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Matsubayashi, Toshimitsu Obonai, Noritaka Ishihara, Shunpei Yamazaki
  • Patent number: 9876118
    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 23, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Shinpei Matsuda, Daisuke Matsubayashi
  • Patent number: 9871145
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: January 16, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Patent number: 9859268
    Abstract: A content addressable memory has many elements in one memory cell; thus, the area of one memory cell tends to be large. In view of the above, it is an object of an embodiment of the present invention to reduce the area of one memory cell. Charge can be held with the use of a channel capacitance in a reading transistor (capacitance between a gate electrode and a channel formation region). In other words, the reading transistor also serves as a charge storage transistor. One of a source and a drain of a charge supply transistor is electrically connected to a gate of the reading and charge storage transistor.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 9847429
    Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yoshiyuki Kobayashi
  • Patent number: 9842940
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: December 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Yoshiyuki Kobayashi, Daisuke Matsubayashi
  • Patent number: 9812458
    Abstract: A memory device that is as small in area as possible and has an extremely long data retention period. A transistor with extremely low leakage current is used as a cell transistor of a memory element in a memory device. Moreover, in order to reduce the area of a memory cell, the transistor is formed so that its source and drain are stacked in the vertical direction in a region where a bit line and a word line intersect each other. Further, a capacitor is stacked above the transistor.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 7, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 9806200
    Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a first insulator, a second insulator, a semiconductor, and a conductor. The semiconductor is over the first insulator. The second insulator is over the semiconductor. The conductor is over the second insulator. The semiconductor includes a first region, a second region, and a third region. The first region is a region where the semiconductor overlaps with the conductor. Each of the second region and the third region is a region where the semiconductor does not overlap with the conductor. The second region and the third region each have a region with a spinel crystal structure.
    Type: Grant
    Filed: March 22, 2016
    Date of Patent: October 31, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Tetsuhiro Tanaka, Masayuki Kimura, Ryo Tokumaru, Daisuke Matsubayashi, Yasumasa Yamane
  • Publication number: 20170309750
    Abstract: A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Yoshiyuki KOBAYASHI, Shinpei MATSUDA, Daisuke MATSUBAYASHI, Hiroyuki TOMISU
  • Publication number: 20170309752
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film.
    Type: Application
    Filed: April 17, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Ryo TOKUMARU, Yasumasa YAMANE, Kiyofumi OGINO, Taichi ENDO, Hajime KIMURA
  • Publication number: 20170309732
    Abstract: Provided is a semiconductor device having favorable reliability.
    Type: Application
    Filed: April 20, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Kazutaka KURIKI, Yuji EGI, Hiromi SAWAI, Yusuke NONAKA, Noritaka ISHIHARA, Daisuke MATSUBAYASHI
  • Publication number: 20170288064
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Daigo ITO, Daisuke MATSUBAYASHI, Masaharu NAGAI, Yoshiaki YAMAMOTO, Takashi HAMADA, Yutaka OKAZAKI, Shinya SASAGAWA, Motomu KURATA, Naoto YAMADE
  • Publication number: 20170278975
    Abstract: The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate electrode layer. In the transistor, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the thickness of the gate insulating film is large (equivalent oxide thickness which is obtained by converting into a thickness of silicon oxide containing nitrogen is 5 nm or more and 50 nm or less, preferably 10 nm or more and 40 nm or less). Alternatively, the channel length is small (5 nm or more and less than 60 nm, preferably 10 nm or more and 40 nm or less), and the resistivity of the source region and the drain region is 1.9×10?5 ?·m or more and 4.8×10?3 ?·m or less.
    Type: Application
    Filed: March 30, 2017
    Publication date: September 28, 2017
    Inventors: Shunpei YAMAZAKI, Daisuke MATSUBAYASHI, Yutaka OKAZAKI
  • Publication number: 20170271523
    Abstract: Provided is a semiconductor device in which deterioration of electric characteristics which becomes more noticeable as the semiconductor device is miniaturized can be suppressed. The semiconductor device includes a first oxide film, an oxide semiconductor film over the first oxide film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a second oxide film over the oxide semiconductor film, the source electrode, and the drain electrode, a gate insulating film over the second oxide film, and a gate electrode in contact with the gate insulating film. A top end portion of the oxide semiconductor film is curved when seen in a channel width direction.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Inventors: Kazuya HANAOKA, Daisuke MATSUBAYASHI, Yoshiyuki KOBAYASHI, Shunpei YAMAZAKI, Shinpei MATSUDA
  • Publication number: 20170263774
    Abstract: A transistor having favorable electrical characteristics. A transistor suitable for miniaturization. A transistor having a high switching speed. One embodiment of the present invention is a semiconductor device that includes a transistor. The transistor includes an oxide semiconductor, a gate electrode, and a gate insulator. The oxide semiconductor includes a first region in which the oxide semiconductor and the gate electrode overlap with each other with the gate insulator positioned therebetween. The transistor has a threshold voltage higher than 0 V and a switching speed lower than 100 nanoseconds.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Daisuke MATSUBAYASHI, Yoshiyuki KOBAYASHI, Shuhei NAGATSUKA, Yutaka SHIONOIRI
  • Patent number: 9754980
    Abstract: An imaging device with excellent imaging performance is provided. An imaging device that easily performs imaging under a low illuminance condition is provided. A low power consumption imaging device is provided. An imaging device with small variations in characteristics between its pixels is provided. A highly integrated imaging device is provided. A photoelectric conversion element includes a first electrode, and a first layer, a second layer, and a third layer. The first layer is provided between the first electrode and the third layer. The second layer is provided between the first layer and the third layer. The first layer contains selenium. The second layer contains a metal oxide. The third layer contains a metal oxide and also contains at least one of a rare gas atom, phosphorus, and boron. The selenium may be crystalline selenium. The second layer may be a layer of an In—Ga—Zn oxide including c-axis-aligned crystals.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yusuke Nonaka, Riho Kataishi, Hiroshi Ohki, Yuichi Sato, Daisuke Matsubayashi
  • Patent number: 9754971
    Abstract: A semiconductor device includes a dual-gate transistor including an oxide semiconductor film between a first gate electrode and a second gate electrode, a gate insulating film between the oxide semiconductor film and the second gate electrode, and a pair of electrodes in contact with the oxide semiconductor film. The semiconductor device further includes an insulating film over the gate insulating film, and a conductive film over the insulating film and connected to one of the pair of electrodes. The insulating film includes an opening in at least a region overlapping with the oxide semiconductor film in which the second gate electrode is provided in contact with the gate insulating film. The second gate electrode is formed using the same material as the conductive film connected to the one of the pair of electrodes.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: September 5, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroyuki Miyake, Seiko Inoue, Daisuke Matsubayashi
  • Publication number: 20170243981
    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.
    Type: Application
    Filed: March 6, 2017
    Publication date: August 24, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko HAYAKAWA, Shinpei MATSUDA, Daisuke MATSUBAYASHI