Patents by Inventor Daisuke Matsubayashi

Daisuke Matsubayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160218106
    Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.
    Type: Application
    Filed: April 5, 2016
    Publication date: July 28, 2016
    Inventor: Daisuke MATSUBAYASHI
  • Patent number: 9401432
    Abstract: A semiconductor device of one embodiment of the present invention includes a semiconductor, an insulator, a first conductor, and a second conductor. In the semiconductor device, a top surface of the semiconductor has a region in contact with the insulator; a side surface of the semiconductor has a region in contact with the insulator; the first conductor has a first region overlapping with the semiconductor with the insulator positioned therebetween; the first region has a region in contact with the top surface of the semiconductor and a region in contact with the side surface of the semiconductor; the second conductor has a second region in contact with the semiconductor; and the first region and the second region do not overlap with each other.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: July 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kobayashi, Daisuke Matsubayashi
  • Patent number: 9391096
    Abstract: To provide a highly reliable semiconductor device. The semiconductor device includes a first oxide layer over an insulating film; an oxide semiconductor layer over the first oxide layer; a gate insulating film over the oxide semiconductor layer; and a gate electrode over the gate insulating film. The first oxide layer contains indium. The oxide semiconductor layer contains indium and includes a channel formation region. The distance from the interface to the channel formation region is 20 nm or more, preferably 30 nm or more, further preferably 40 nm or more, still further preferably 60 nm or more.
    Type: Grant
    Filed: January 14, 2014
    Date of Patent: July 12, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Hideomi Suzawa, Tetsuhiro Tanaka, Hirokazu Watanabe
  • Patent number: 9385128
    Abstract: A selection operation is performed for individual memory cells. A device includes a first memory cell and a second memory cell provided in the same row as the first memory cell, each of which includes a field-effect transistor having a first gate and a second gate. The field-effect transistor controls at least data writing and data holding in the memory cell by being turned on or off. The device further includes a row selection line electrically connected to the first gates of the field-effect transistors included in the first memory cell and the second memory cell, a first column selection line electrically connected to the second gate of the field-effect transistor included in the first memory cell, and a second column selection line electrically connected to the second gate of the field-effect transistor included in the second memory cell.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Publication number: 20160190347
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Shinya SASAGAWA, Motomu KURATA, Kazuya HANAOKA, Yoshiyuki KOBAYASHI, Daisuke MATSUBAYASHI
  • Publication number: 20160190338
    Abstract: To provide a semiconductor device suitable for high reliability and high-speed operation. The semiconductor device includes a first conductor, a first insulator, a second insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The first conductor includes a region overlapping with the channel formation region with the first insulator provided therebetween. The second insulator is placed to include a region in contact with a side surface of the first conductor. The electron trap layer is placed to face the first conductor with the second insulator provided therebetween.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 30, 2016
    Inventors: Tetsuhiro TANAKA, Daisuke MATSUBAYASHI, Kazuki TANEMURA
  • Publication number: 20160190348
    Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Junichi KOEZUKA, Yukinori SHIMA, Hajime TOKUNAGA, Toshinari SASAKI, Keisuke MURAYAMA, Daisuke MATSUBAYASHI
  • Publication number: 20160181438
    Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
    Type: Application
    Filed: March 1, 2016
    Publication date: June 23, 2016
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke MATSUBAYASHI, Yoshiyuki KOBAYASHI
  • Publication number: 20160149045
    Abstract: A semiconductor device includes a first conductor, a second conductor, a first insulator, a second insulator, a third insulator, a semiconductor, and an electron trap layer. The semiconductor includes a channel formation region. The electron trap layer overlaps with the channel formation region with the second insulator interposed therebetween. The first conductor overlaps with the channel formation region with the first insulator interposed therebetween. The second conductor overlaps with the electron trap layer with the third insulator interposed therebetween. The second conductor does not overlap with the channel formation region.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 26, 2016
    Inventors: Tetsuhiro TANAKA, Daisuke MATSUBAYASHI, Kazuki TANEMURA
  • Patent number: 9349869
    Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve the electrical characteristics and the reliability of a semiconductor device including an oxide semiconductor film. In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: May 24, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Publication number: 20160141422
    Abstract: A semiconductor device in which deterioration of electrical characteristics which becomes more noticeable as the transistor is miniaturized can be suppressed is provided. The semiconductor device includes an oxide semiconductor stack in which a first oxide semiconductor layer, a second oxide semiconductor layer, and a third oxide semiconductor layer are stacked in this order from the substrate side over a substrate; a source electrode layer and a drain electrode layer which are in contact with the oxide semiconductor stack; a gate insulating film over the oxide semiconductor stack, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating film. The first oxide semiconductor layer includes a first region. The gate insulating film includes a second region. When the thickness of the first region is TS1 and the thickness of the second region is TG1, TS1?TG1.
    Type: Application
    Filed: January 20, 2016
    Publication date: May 19, 2016
    Inventors: Daisuke Matsubayashi, Satoshi Shinohara, Wataru Sekine
  • Publication number: 20160141089
    Abstract: A multilayer inductor providing improved DC superposition characteristics by a permanent magnet that emits a bias magnetic flux, and having a low-loss material as a magnetic body to improve converter conversion efficiency. The multilayer inductor has a plurality of laminated electrically insulating magnetic layers; and laminated conductive patterns, each of the conductive patterns being connected in sequence in the lamination direction forming a spiral coil inside the magnetic layer. An magnetized annular permanent magnet layer emits a magnetic flux whose direction is opposite that of a magnetic flux excited by the coil is between an outer peripheral edge of the inductor and an outer peripheral edge of the coil so as not to overlap an inner peripheral part of the magnet layer with the conductive patterns and so as to block a space between the conductive patterns and the magnet layer, in axial view of the coil.
    Type: Application
    Filed: May 16, 2014
    Publication date: May 19, 2016
    Applicant: FDK Corporation
    Inventors: Kiyohisa YAMAUCHI, Daisuke MATSUBAYASHI, Juji KATO, Mikio KITAOKA, Shigenori SUZUKI
  • Patent number: 9324876
    Abstract: A semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with side surfaces of the first oxide semiconductor film, side surfaces of the second oxide semiconductor film, and the top surface of the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the top surface of the gate insulating film. A length obtained by subtracting a channel length between the source electrode and the drain electrode from a length of the second oxide semiconductor film in the channel length direction is 0.2 times to 2.0 times as long as the channel length.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: April 26, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki Kobayashi, Daisuke Matsubayashi
  • Patent number: 9318484
    Abstract: The semiconductor device of the present invention comprises first and second transistors and first and second capacitors. One of source and drain electrodes of the first transistor is electrically connected to a first wiring, the other is electrically connected to a second wiring, and a gate electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor and one of electrodes of the first capacitor. The other of the source and drain electrodes of the second transistor is electrically connected to the first wiring, and a gate electrode of the second transistor is electrically connected to one of electrodes of a second capacitor and a fifth wiring. The other electrode of the first capacitor is electrically connected to a third wiring, and the other electrode of the second capacitor is eclectically connected to a fourth wiring.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: April 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Daisuke Matsubayashi
  • Patent number: 9312392
    Abstract: A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In the channel width direction of the transistor, a side surface of each of the first and second gate electrodes is on the outer side of a side surface of the oxide semiconductor film. The first or second gate electrode faces the side surface of the oxide semiconductor film with the gate insulating film provided between the first or second gate electrode and the oxide semiconductor film.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: April 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Daisuke Matsubayashi
  • Patent number: 9306074
    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 ?m or longer and 6.5 ?m or shorter.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: April 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Shinpei Matsuda, Daisuke Matsubayashi
  • Patent number: 9287410
    Abstract: A semiconductor device with favorable electrical characteristics is provided. The semiconductor device includes an insulating layer, a semiconductor layer over the insulating layer, a source electrode layer and a drain electrode layer electrically connected to the semiconductor layer, a gate insulating film over the semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer overlapping with part of the semiconductor layer, part of the source electrode layer, and part of the drain electrode layer with the gate insulating film therebetween. A cross section of the semiconductor layer in the channel width direction is substantially triangular or substantially trapezoidal. The effective channel width is shorter than that for a rectangular cross section.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Motomu Kurata, Kazuya Hanaoka, Yoshiyuki Kobayashi, Daisuke Matsubayashi
  • Patent number: 9287411
    Abstract: In a semiconductor device including a transistor including a gate electrode formed over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, a first oxide insulating film covering the transistor, and a second oxide insulating film formed over the first oxide insulating film, the multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide semiconductor film has an amorphous structure or a microcrystalline structure, the first oxide insulating film is an oxide insulating film through which oxygen is permeated, and the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric composition.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichi Koezuka, Yukinori Shima, Hajime Tokunaga, Toshinari Sasaki, Keisuke Murayama, Daisuke Matsubayashi
  • Publication number: 20160071840
    Abstract: A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region.
    Type: Application
    Filed: September 1, 2015
    Publication date: March 10, 2016
    Inventors: Yoshitaka YAMAMOTO, Masayuki SAKAKURA, Tetsuhiro TANAKA, Daisuke MATSUBAYASHI
  • Patent number: 9281409
    Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: March 8, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yoshiyuki Kobayashi