Patents by Inventor Daisuke Matsushita

Daisuke Matsushita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11956146
    Abstract: A reception unit (210) receives an addition requesting frame for requesting addition of a new flow. A first search unit (241) performs, using a network-information database (280), a first search for searching for a schedule and a path assignable to the new flow without the schedule and the path of each existing flow being changed, when the addition requesting frame is received. A second search unit (242) performs a second search for changing the schedule and the path of each existing flow and searching for the schedule and the path assignable to the new flow, using the network-information database, when the schedule and the path assignable to the new flow have not been found by the first search. A response unit (260) transmits an addition responding frame.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: April 9, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Makoto Kubomi, Ryuma Matsushita, Daisuke Takita, Yoshifumi Hotta
  • Patent number: 11945923
    Abstract: Disclosed is a method for producing an electrolytic capacitor, the method including the steps of preparing an anode foil that includes a dielectric layer, a cathode foil, and a fiber structure; preparing a conductive polymer dispersion liquid that contains a conductive polymer component and a dispersion medium; producing a separator by applying the conductive polymer dispersion liquid to the fiber structure and then removing at least a portion of the dispersion medium; and producing a capacitor element by sequentially stacking the anode foil, the separator, and the cathode foil. The dispersion medium contains water. The fiber structure contains a synthetic fiber in an amount of 50 mass % or more. The fiber structure has a density of 0.2 g/cm3 or more and less than 0.45 g/cm3.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: April 2, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Daisuke Kubo, Hiroyuki Arima, Tomoyuki Tashiro, Kazuhiro Takatani, Kenta Chashiro, Shumpei Matsushita
  • Patent number: 11947304
    Abstract: A cleaning device includes: a cleaning brush that has bristles that rotate and contact a surface, to which toner has adhered, of a cleaning member to be cleaned, the cleaning brush removing the toner adhered to the surface of the cleaning member; a first contact member that contacts the bristles without a position of the first contact member relative to a position of the cleaning brush being changed; and a second contact member that contacts the bristles at a location downstream from the first contact member in a direction of rotation of the cleaning brush and without a position of the second contact member relative to the position of the cleaning brush being changed, and that is disposed on an extension line extended from a line between an axial center of the cleaning brush and a base of the bristles that move away from the first contact member.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Haruyuki Ideura, Daisuke Tanaka, Takeshi Yasuda, Kaoru Matsushita
  • Patent number: 10631450
    Abstract: A component mounting system reduces the waste of components while mounting components via an application material. The system determines whether or not to permit the start of the mounting process to a plurality of applying locations based on the post-application elapsed time that has elapsed after the application of the adhesive to the applying location. That is, the system predicts the post-application elapsed time exceeds the time limit at the mounting timing at which the component is mounted in the mounting process for each applying location. If the plurality of applying locations include no applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is permitted. However, if there is any applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is prohibited.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: April 21, 2020
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Daisuke Matsushita, Daisuke Kasuga
  • Publication number: 20200066748
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body in which a plurality of insulating layers and a plurality of conductive layers are alternately stacked above a substrate, a pillar that penetrates the stacked body while extending in a stacking direction of the stacked body, and a semiconductor layer, a first insulating layer, a charge accumulation layer, and a second insulating layer, which are stacked on a side surface of the pillar in order from the pillar, wherein the semiconductor layer has an average grain size that is larger on a side nearer to the pillar and is smaller on a side nearer to the first insulating layer.
    Type: Application
    Filed: December 4, 2018
    Publication date: February 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Daisuke MATSUSHITA, Yui KAGI, Tatsuya FUJISHIMA, Masayuki SHISHIDO, Nozomi KIDO, Tomonori KAJINO, Nobuhito KUGE
  • Publication number: 20180199476
    Abstract: A component mounting system reduces the waste of components while mounting components via an application material. The system determines whether or not to permit the start of the mounting process to a plurality of applying locations based on the post-application elapsed time that has elapsed after the application of the adhesive to the applying location. That is, the system predicts the post-application elapsed time exceeds the time limit at the mounting timing at which the component is mounted in the mounting process for each applying location. If the plurality of applying locations include no applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is permitted. However, if there is any applying location where the post-application elapsed time exceeds the time limit at the mounting timing, the start of the mounting process is prohibited.
    Type: Application
    Filed: July 10, 2015
    Publication date: July 12, 2018
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Daisuke MATSUSHITA, Daisuke KASUGA
  • Patent number: 9966736
    Abstract: A spark plug having a center electrode, a ground electrode, and a noble metal tip that is joined to a part of the ground electrode near one end of the ground electrode via a fused portion. The fused portion extends outward beyond an outer shape of the noble metal tip so that a part of the fused portion is present at each of positions that are located inward from and separated from both side edges of the ground electrode in a width direction of the ground electrode. The fused portion includes a fused protrusion that is located near at least one of two side edges of the noble metal tip in the width direction of the ground electrode and that protrudes in a direction away from the one end of the ground electrode.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: May 8, 2018
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Daisuke Matsushita, Masahiro Inoue
  • Patent number: 9935122
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
  • Patent number: 9928908
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Reika Ichihara, Daisuke Matsushita, Shosuke Fujii
  • Patent number: 9865606
    Abstract: According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a second conductivity type in the semiconductor region; a gate electrode above a first part of the semiconductor region between the first region and the second region; a gate insulating layer between the first part and the gate electrode; a third region having the first conductivity type below the second region; and a fourth region across the second region and the third region and including a first impurity.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: January 9, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chika Tanaka, Daisuke Matsushita
  • Publication number: 20170294763
    Abstract: A spark plug having a center electrode, a ground electrode, and a noble metal tip that is joined to a part of the ground electrode near one end of the ground electrode via a fused portion. The fused portion extends outward beyond an outer shape of the noble metal tip so that a part of the fused portion is present at each of positions that are located inward from and separated from both side edges of the ground electrode in a width direction of the ground electrode. The fused portion includes a fused protrusion that is located near at least one of two side edges of the noble metal tip in the width direction of the ground electrode and that protrudes in a direction away from the one end of the ground electrode.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 12, 2017
    Applicant: NGK SPARK PLUG CO., LTD.
    Inventors: Daisuke MATSUSHITA, Masahiro INOUE
  • Patent number: 9780170
    Abstract: A semiconductor memory device of an embodiment comprises a memory cell. This memory cell comprises: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between the oxide semiconductor layer and the gate electrode. This oxide semiconductor layer includes a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor layer.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: October 3, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kensuke Ota, Toshifumi Irisawa, Tomoya Kawai, Daisuke Matsushita, Tsutomu Tezuka
  • Publication number: 20170271466
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.
    Type: Application
    Filed: September 15, 2016
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Daisuke MATSUSHITA, Yasushi NAKASAKI, Tsunehiro INO
  • Patent number: 9768265
    Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage layer. The first oxide layer is provided between the semiconductor layer and the first electrode. The second oxide layer is provided between the first oxide layer and the first electrode. The storage layer is provided between the first and second oxide layers. The storage layer includes a first region including silicon nitride, a second region provided between the first region and the second oxide layer and including silicon nitride, and a third region provided between the first and second regions. The third region includes a plurality of first metal atoms. A first density of bond of the first metal atoms in the third region is lower than a second density of bond of the first metal atom and a nitrogen atom in the third region.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Matsushita, Yasushi Nakasaki, Tsunehiro Ino
  • Patent number: 9728881
    Abstract: A connector terminal includes first and second arm parts, an interconnection part, a first contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are present, and a second contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are located, and the second contactor facing the first contactor.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: August 8, 2017
    Assignee: DAI-ICHI SEIKO CO., LTD.
    Inventors: Takayoshi Endo, Jun Mukunoki, Daisuke Matsushita
  • Patent number: 9698236
    Abstract: It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: July 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Daisuke Matsushita, Yuuichiro Mitani
  • Patent number: 9691973
    Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 27, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro Ino, Riichiro Takaishi, Koichi Kato, Yasushi Nakasaki, Takamitsu Ishihara, Daisuke Matsushita
  • Patent number: 9685462
    Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer including a first region, a second region and the third region provided between the first region and the second region. The oxide semiconductor layer contains indium (In), gallium (Ga), and zinc (Zn). The first and second regions have thinner film thickness and lower indium (In) concentration than the third region. An insulating film is provided on the third region, and an electrode is provided on the insulating film. A first conductive layer is provided under the first region and electrically connected with the first region. A second conductive layer is provided under the second region and electrically connected with the second region.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: June 20, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kensuke Ota, Masumi Saitoh, Kiwamu Sakuma, Daisuke Matsushita, Chika Tanaka
  • Publication number: 20170148516
    Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Reika ICHIHARA, Daisuke MATSUSHITA, Shosuke FUJII
  • Publication number: 20170125934
    Abstract: A connector terminal includes first and second arm parts, an interconnection part, a first contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are present, and a second contactor formed of a piece of sheet which is in a bent shape so as to have the first end laid over on a second end of the sheet with reference to a bent part that is an opposite side to a side where the first end of the sheet and the second end thereof are located, and the second contactor facing the first contactor.
    Type: Application
    Filed: October 27, 2016
    Publication date: May 4, 2017
    Inventors: Takayoshi Endo, Jun Mukunoki, Daisuke Matsushita