Abstract: Provided are a crystal element and a crystal device that have an improved DLD characteristic. The crystal element includes a crystal piece and a pair of electrodes. Each of the electrodes is positioned on a corresponding one of both surfaces of the crystal piece and includes a conductive layer having a gold content of 90% or more in mass ratio. The crystal element has the DLD characteristic in which a portion in a positive direction (+) and a portion in an opposite direction (?) are mixed.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 ?/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 ?m when viewed at a viewing angle of 120°.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: There is provided a conveying device that can support a car weight with a mechanism lighter in weight. A driving device (6) of a conveying device that lifts and lowers a loading-weight support along a rail (3) includes a wheel unit (13) and a link (14). The wheel unit (13) drives to rotate a driving wheel (15) in contact with a guide surface (11) to lift and lower the loading-weight support. The link (14) includes a first joint (17) connected to the wheel unit (13) and a second joint (18) rotatably supported by the loading-weight support. The second joint (18) is arranged in a position further apart from the guide surface (11) than the first joint (17), and above the first joint (17). The link (14) is arranged such that a straight line connecting the first joint (17) and the second joint (18) is tilted smaller than 45 degrees.

Abstract: A wiring board (10) includes a substrate (11) that is transparent, a wiring pattern region (20) disposed on the substrate (11) and having first-direction wiring lines (21), and a feeding unit (40) electrically connected to the first-direction wiring lines (21) of the wiring pattern region (20). Each first-direction wiring line (21) has a first region (26) positioned near the feeding unit (40) and a second region (27) that is a region other than the first region (26). A line width (W3) of the first-direction wiring line (21) in the first region (26) is larger than a line width (W1) of the first-direction wiring line (21) in the second region (27).

Abstract: The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Abstract: A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 ?/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 ?m when viewed at a viewing angle of 120°.

Abstract: A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Abstract: The purpose of the invention is to compensate for the radiation tolerance of a semiconductor memory. An apparatus (10) for compensating for radiation tolerance comprises: a voltage value acquisition unit (11) that acquires a data retention voltage value that is a maximum voltage value at which data is inverted when a power supply voltage of a semiconductor memory having a latch circuit is lowered; a correction value determination unit (12) that determines a voltage correction value on the basis of a difference between the data retention voltage value and a reference voltage value; and a voltage adjustment unit (13) that adjusts at least one among the power supply voltage and a substrate bias voltage by using the voltage correction value. The reference voltage value is set to be equal to or lower than the data retention voltage value that satisfies a required radiation tolerance.

Abstract: A semiconductor device includes first to N-th PLL circuits configured to operate in synchronization with a common reference clock signal to output first to N-th clock signals, respectively; a majority circuit that performs a majority operation on the first to N-th clock signals to generate a majority clock signal; and a filter circuit to which the majority clock signal is provided, the filter circuit operating as a low-pass filter to output an output clock signal. N is an odd number of three or more.

Abstract: A wiring board includes: a substrate having transparency; a plurality of first wirings which are arranged on an upper surface of the substrate and extend in a first direction and each of which has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface; and has a back surface in contact with the substrate and a front surface facing an opposite side of the back surface. The first wiring has a pair of side surfaces which extend in the first direction and are adjacent to the back surface of the first wiring, and each of the pair of side surfaces of the second wiring is recessed inward. The second wiring has a pair of side surfaces which extend in the second direction and are adjacent to the back surface of the second wiring.

Abstract: An operation adjustment method of an SOI device comprises steps of: (a) obtaining a drain current-substrate bias voltage characteristic of an NMOS transistor for a source-gate voltage of 0V; (b) obtaining a lowest substrate bias voltage which turns on the NMOS transistor from the drain current-substrate bias voltage characteristic; (c) determining an upper limit of a substrate bias voltage of a PMOS transistor as a voltage obtained by subtracting a built-in potential of a pn junction from the lowest substrate bias voltage; and (d) determining the substrate bias voltage of the PMOS transistor as a positive voltage lower than the upper limit. Reduction in the power consumption and maintenance of the radiation tolerance are both achieved for the SOI device.

Abstract: Provided is an electrical connection box that is equipped with a newly constructed dark current circuit connection/disconnection mechanism that can be used to change circuits of the dark current circuit connection/disconnection mechanism and improve versatility. A conduction member holder has a conduction member holding portion that extends spanning over a plurality of cavities that are provided in a case. A conduction member includes: a first conduction member that is connected to a connection terminal of a dark current circuit housed in one of the cavities; and a second conduction member that is connected simultaneously to the connection terminal of the dark current circuits housed in one of the cavities and a connection terminal of another circuit housed in another cavity. The first conduction member or the second conduction member that is selected according to a required circuit configuration is mounted in the conduction member holding portion.

Abstract: Provided is a novel dark-current-circuit interruption structure that can stably maintain the state of engagement of an engaging portion of a conductive component holder with an engaged portion of a case, while reducing the size of the case, and an electrical junction box including the same. A conductive component is formed by a plate metal fitting, a conductive component holder 48 includes elastic projecting pieces and engaging portions that are provided on each of a pair of side walls that are opposingly positioned with a gap between the plate metal fitting and each of the side walls, and the case includes engaged portions with which the engaging portions are to be engaged. When attaching the conductive component holder to the case, the engaging portions and the engaged portions are configured to come into contact with each other to cause the elastic projecting pieces 68 and 76 to elastically deform.

Abstract: An electrical connection box includes a box main body; internal circuits that are arranged and accommodated in the box main body; and a terminal fastening portion that is arranged and accommodated in the box main body, and that is provided with a first fastening tool, the electrical connection box having a plurality of connection terminal portions that are provided to the internal circuits arranged on a first seating surface of the first fastening tool, and also having the plurality of connection terminal portions fastened and fixed together with a connection terminal that is crimped to an end of an external wire, in which the plurality of connection terminal portions each include a plurality of divided terminal portions that are formed to a size that partially covers the first seating surface of the first fastening tool and do not overlap each other in an axis direction of the first fastening tool.

Abstract: Provided is an electrical junction box with which it is possible to reliably prevent exposure to the outside of the entire L-shaped terminal that is fastened to a stud bolt conductively connected to a conductive member of a box body even when an upper cover is removed, while making it easier to fasten the L-shaped terminal to the stud bolt. A terminal cover is hingedly connected to a box body, is pivotable about hinge portions between an open state and a closed state, and includes a top cover that covers a bolt fastening portion, and a side cover that covers a wire connection portion. The side cover includes a front-surface cover wall that covers a wire connection portion from an outer circumference side of a first peripheral wall portion, and a side-surface cover wall that covers a front side surface of two side surfaces of the wire connection portion.

Abstract: Disclosed are: a lactic acid bacterium belonging to Lactobacillus kunkeei, the bacterium having a higher IgA production inducing activity than that of Lactobacillus strain GG (ATCC53103), and a lower mitogenic activity and a lower IL-2 production inducing activity than those of Listeria strain EGD; and a food composition, a pharmaceutical composition, a cosmetic composition, an immunostimulant for preventing the infection by pathogens or viruses that invade through the respiratory or esophageal mucosa, and an intestinal immunostimulant for preventing or alleviating food poisoning, each of which contains the lactic acid bacterium or treated cells of the lactic acid bacterium.