Patents by Inventor Daisuke Okada

Daisuke Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9825049
    Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.
    Type: Grant
    Filed: January 16, 2016
    Date of Patent: November 21, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Naohiro Hosoda, Daisuke Okada, Kozo Katayama
  • Publication number: 20170229469
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Application
    Filed: April 28, 2017
    Publication date: August 10, 2017
    Inventors: Tsutomu OKAZAKI, Daisuke OKADA, Kyoya NITTA, Toshihiro TANAKA, Akira KATO, Toshikazu MATSUI, Yasushi ISHII, Digh HISAMOTO, Kan YASUI
  • Patent number: 9640546
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 2, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Patent number: 9628665
    Abstract: An information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus includes an acquisition part creating a first information request, a first transmitter transmitting the first information request to the second information processing apparatus, a first receiver receiving the first information from the second information processing apparatus, a display controller controlling displaying the first information, and a first storage storing second information, the display controller controlling displaying the second information when the second information is stored in the first storage.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 18, 2017
    Assignee: Ricoh Company, Ltd.
    Inventors: Daisuke Okada, Hiroya Uruta, Yuka Saito, Akiko Kitayama, Yuto Shibata, Chan Gu, Keisuke Nakazawa
  • Patent number: 9589638
    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: March 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Patent number: 9558826
    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 31, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Publication number: 20160379713
    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.
    Type: Application
    Filed: May 11, 2016
    Publication date: December 29, 2016
    Inventors: Tsuyoshi ARIGANE, Daisuke Okada, Digh Hisamoto
  • Patent number: 9515082
    Abstract: A memory gate is formed of a first memory gate including a second gate insulating film made of a second insulating film and a first memory gate electrode, and a second memory gate including a third gate insulating film made of a third insulating film and a second memory gate electrode. In addition, the lower surface of the second memory gate electrode is located lower in level than the lower surface of the first memory gate electrode. As a result, during an erase operation, an electric field is concentrated on the corner portion of the first memory gate electrode which is located closer to a selection gate and a semiconductor substrate and on the corner portion of the second memory gate electrode which is located closer to the first memory gate and the semiconductor substrate. This allows easy injection of holes into each of the second and third insulating films.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: December 6, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Digh Hisamoto, Daisuke Okada
  • Patent number: 9508837
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Grant
    Filed: January 24, 2016
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Patent number: 9508554
    Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuharu Yamabe, Shinichiro Abe, Shoji Yoshida, Hideaki Yamakoshi, Toshio Kudo, Seiji Muranaka, Fukuo Owada, Daisuke Okada
  • Publication number: 20160155093
    Abstract: A main body of the image forming apparatus includes a first user-information storage unit configured to store user information. An information processing terminal includes: a data processing unit configured to acquire attendance information; a user-information processing unit configured to acquire, from the main body of the image forming apparatus, user information of a user who has clocked in determined based on the attendance information and acquire user information read in by the reader from the user-information recording medium for user authentication; and, a second user-information storage unit configured to store the user information of the user who has clocked in. The user-information processing unit being configured to perform user authentication by using the user information stored by the second user-information storage unit and the user information read in by the reader from the user-information recording medium for user authentication.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 2, 2016
    Applicant: Ricoh Company, Limited
    Inventors: Yuto SHIBATA, Daisuke OKADA, Chan GU, Keisuke NAKAZAWA, Hiroya URUTA, Akiko KITAYAMA, Yuka SAITO
  • Publication number: 20160150123
    Abstract: An information processing system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus includes an acquisition part creating a first information request, a first transmitter transmitting the first information request to the second information processing apparatus, a first receiver receiving the first information from the second information processing apparatus, a display controller controlling displaying the first information, and a first storage storing second information, the display controller controlling displaying the second information when the second information is stored in the first storage.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 26, 2016
    Applicant: Ricoh Company, Ltd.
    Inventors: Daisuke OKADA, Hiroya URUTA, Yuka SAITO, Akiko KITAYAMA, Yuto SHIBATA, Chan GU, Keisuke NAKAZAWA
  • Publication number: 20160141396
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Application
    Filed: January 24, 2016
    Publication date: May 19, 2016
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Publication number: 20160133641
    Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.
    Type: Application
    Filed: January 16, 2016
    Publication date: May 12, 2016
    Inventors: Naohiro HOSODA, Daisuke OKADA, Kozo KATAYAMA
  • Publication number: 20160093499
    Abstract: To provide a semiconductor device having improved performance while improving the throughput in the manufacturing steps of the semiconductor device. An insulating film portion comprised of first, second, third, fourth, and fifth insulating films is formed on a semiconductor substrate. The second insulating film is a first charge storage film and the fourth insulating film is a second charge storage film. The first charge storage film contains silicon and nitrogen; the third insulating film contains silicon and oxygen; and the second charge storage film contains silicon and nitrogen. The thickness of the third insulating film is smaller than that of the first charge storage film and the thickness of the second charge storage film is greater than that of the first charge storage film. The third insulating film is formed by treating the upper surface of the first charge storage film with a water-containing treatment liquid.
    Type: Application
    Filed: September 29, 2015
    Publication date: March 31, 2016
    Inventors: Kazuharu YAMABE, Shinichiro ABE, Shoji YOSHIDA, Hideaki YAMAKOSHI, Toshio KUDO, Seiji MURANAKA, Fukuo OWADA, Daisuke OKADA
  • Publication number: 20160071858
    Abstract: Provided is a semiconductor device having improved performance. The semiconductor device includes the memory cells of a flash memory. Each of the memory cells includes a capacitor element for writing/erasing data having a gate electrode formed of a part of a floating gate electrode, and a MISFET for reading data having a gate electrode formed of another part of the floating gate electrode. The capacitor element for writing/erasing data has a p-type semiconductor region and an n-type semiconductor region which have opposite conductivity types. The length of the floating gate electrode in a gate length direction in the capacitor element for writing/erasing data is smaller than the length of the floating gate electrode in the gate length direction in the MISFET for reading data.
    Type: Application
    Filed: November 16, 2015
    Publication date: March 10, 2016
    Inventors: Hideaki Yamakoshi, Daisuke Okada
  • Publication number: 20160072977
    Abstract: An information processing apparatus includes an address information storage storing recipient information relating to a recipient and the recipient's address with an address identifier as address information; a program storage storing setting information in association with a program identifier as program information, the setting information including program identification information specifying a program and the address identifier; a program execution unit executing the program associated with the program identifier based on the setting information; an address information change unit changing the address information in the address information storage, and changing the address identifier along with the change in the address information; and an information change adjusting unit adjusting, upon detecting a change in one of the address identifier and the address information, the address identifier of the program information including the address identifier in the program storage in response to the change in the
    Type: Application
    Filed: September 1, 2015
    Publication date: March 10, 2016
    Applicant: Ricoh Company, Ltd.
    Inventors: Kazuki SASAYAMA, Daisuke OKADA, Chan GU, Yuto SHIBATA, Akiko KITAYAMA, Daisuke MASUI, Masashi TANIGUCHI, Noboru TAMURA, Naoya TAMURA, Yuka SAITO, Hiroya URUTA
  • Patent number: 9257446
    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 9, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuyoshi Arigane, Daisuke Okada, Digh Hisamoto
  • Patent number: 9245900
    Abstract: A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second insulating film formed between a memory gate electrode and the semiconductor substrate and between the control gate electrode and the memory gate electrode, the second insulating film having a charge accumulating part therein. The second insulating film has a first film, a second film serving as a charge accumulating part disposed on the first film, and a third film disposed on the second film. The third film has a sidewall film positioned between the control gate electrode and the memory gate electrode and a deposited film positioned between the memory gate electrode and the semiconductor substrate. In this structure, the distance at a corner part of the second insulating film can be increased, and electric-field concentration can be reduced.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: January 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Naohiro Hosoda, Daisuke Okada, Kozo Katayama
  • Publication number: 20150339548
    Abstract: A processing function proposing apparatus includes a status detector that detects a current status of a resource, a request acquisition unit that acquires a composite function requested to be executed from multiple composite functions, each composite function combining multiple unit functions, a function selecting unit to select at least one unit function combined that executes the requested composite function based on the current status of the resource, and a proposing unit that proposes the unit function selected by the function selecting unit.
    Type: Application
    Filed: May 21, 2015
    Publication date: November 26, 2015
    Inventors: Akiko KITAYAMA, Yasuyuki Igarashi, Daisuke Masui, Daisuke Okada, Yuka Saito, Yuto Shibata, Hiroya Uruta, Naoya Tamura, Noboru Tamura, Kazuki Sasayama, Masashi Taniguchi, Chan Gu