Patents by Inventor Dakshesh D. Parikh

Dakshesh D. Parikh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4893279
    Abstract: A storage device capable of being configured either as a single-access memory or as two separate memories is described. The storage device is especially suited for use in a digital signal processor performing numeric algorithms such as fast fourier transforms, autocorrelation and digital filtering because certain of such algorithms require fast dual access to two correlated, but separate, parameters while other such algorithms require fast single access to identical parameters. The storage device is shown in an exemplary embodiment empolying a multiplexer to affect writing of data from either of two data busses to one of the memories. In a second embodiment the write port of the memory is connected to one bus and the read port is connected to both busses. In this embodiment a dual-port address register file and a pair of address generation units provide indirect addressing capability for the storage device. Method of operating separate memories in a single-access or a dual-access mode is also described.
    Type: Grant
    Filed: February 13, 1989
    Date of Patent: January 9, 1990
    Assignee: Advanced Micro Devices Inc.
    Inventors: Mahboob F. Rahman, Dakshesh D. Parikh, Marita E. Daly, Bu-Chin Wang
  • Patent number: 4811376
    Abstract: A paging system providing an LPC encoded speech output having an adaptive bit rate. The LPC bit rate is adaptively modified based on paging system airtime loading. Synthesizer circuitry in the paging receivers, together with a system signaling scheme is used to update the paging receivers as to the LPC bit rate, allows the paging receiver to decode the adaptive bit rate signal.
    Type: Grant
    Filed: October 16, 1987
    Date of Patent: March 7, 1989
    Assignee: Motorola, Inc.
    Inventors: Walter L. Davis, Dakshesh D. Parikh
  • Patent number: 4701943
    Abstract: A paging system providing an LPC encoded speech output having an adaptive bit rate. The LPC bit rate is adaptively modified based on paging system airtime loading. Synthesizer circuitry in the paging receivers, together with a system signalling scheme is used to update the paging receivers as to the LPC bit rate, allows the paging receiver to decode the adaptive bit rate signal.
    Type: Grant
    Filed: November 12, 1986
    Date of Patent: October 20, 1987
    Assignee: Motorola, Inc.
    Inventors: Walter L. Davis, Dakshesh D. Parikh