Patents by Inventor Dale A. Witte

Dale A. Witte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180117690
    Abstract: A method for producing diamond grits for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated. The intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Omid Rezvanian, Larry Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
  • Patent number: 9873159
    Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 23, 2018
    Assignee: Corner Star Limited
    Inventors: Omid Rezvanian, Larry Wayne Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
  • Patent number: 9499920
    Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: November 22, 2016
    Assignee: MEMC Singapore Pte. Ltd. (UEN200614794D)
    Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
  • Publication number: 20160184909
    Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.
    Type: Application
    Filed: December 30, 2015
    Publication date: June 30, 2016
    Inventors: Omid Rezvanian, Larry Wayne Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
  • Publication number: 20150308011
    Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
  • Patent number: 9111745
    Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the alignment layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 18, 2015
    Assignee: MEMC Singapore Pte., Ltd. (UEN200614794D)
    Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
  • Patent number: 8900972
    Abstract: A method of producing rectangular seed bricks for use in semiconductor or solar manufacturing is disclosed. The method includes connecting an alignment layer to a top surface of a template, drawing alignment lines on the alignment layer to demarcate a plurality of nodes, connecting cylindrical rods to the alignment layer such that a center of each rod is aligned with a corresponding node, and slicing through the rods and the alignment layer with a wire web to produce rectangular seed bricks.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: December 2, 2014
    Assignee: MEMC Singapore Pte. Ltd.
    Inventors: Dale A. Witte, Jihong John Chen, Travis L. Hambach, Linda K. Swiney
  • Patent number: 8859393
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 14, 2014
    Assignee: SunEdison Semiconductor Limited
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Patent number: 8845859
    Abstract: Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: September 30, 2014
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Michael John Ries, Jeffrey L. Libbert, Dale A. Witte
  • Publication number: 20140182776
    Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the alignment layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)
    Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Hayes, Tom Doane, Dale A. Witte, Linda K. Swiney, Travis Hambach
  • Publication number: 20140186486
    Abstract: An apparatus for producing rectangular seeds for use in semiconductor or solar material manufacturing includes a template having a top surface and parallel slots, and an adhesive layer connected to the top surface of the template. The adhesive layer includes alignment lines aligned with the parallel slots. The apparatus also includes quarter sections made of a semiconductor or solar material and connected to the alignment layer. An interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines. A wire web is adapted to slice through the interface of each quarter section to separate the rectangular seed portions from the curved wing portions to produce rectangular seeds.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)
    Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Hayes, Tom Doane, Dale A. Witte, Linda K. Swiney, Travis Hambach
  • Publication number: 20140137794
    Abstract: A method of preparing a directional solidification system (DSS) furnace for use in semiconductor or solar manufacturing includes slicing a plurality of cylindrical rods to produce a plurality of rectangular seed bricks, a plurality of corner portions, and a plurality of quarter sections, and cropping the plurality of rectangular seed bricks into a plurality of rectangular seeds.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)
    Inventors: Dale A. Witte, Jihong John Chen, Travis Hambach, Linda Swiney
  • Publication number: 20140137395
    Abstract: A method of producing rectangular seed bricks for use in semiconductor or solar manufacturing is disclosed. The method includes connecting an alignment layer to a top surface of a template, drawing alignment lines on the alignment layer to demarcate a plurality of nodes, connecting cylindrical rods to the alignment layer such that a center of each rod is aligned with a corresponding node, and slicing through the rods and the alignment layer with a wire web to produce rectangular seed bricks.
    Type: Application
    Filed: November 19, 2012
    Publication date: May 22, 2014
    Applicant: MEMC Singapore, Pte. Ltd (UEN200614797D)
    Inventors: Dale A. Witte, Jihong John Chen, Travis L. Hambach, Linda K. Swiney
  • Publication number: 20130062020
    Abstract: Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.
    Type: Application
    Filed: March 12, 2012
    Publication date: March 14, 2013
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Michael John Ries, Jeffrey L. Libbert, Dale A. Witte
  • Patent number: 8367519
    Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: February 5, 2013
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Dale A. Witte, Jeffrey L. Libbert
  • Publication number: 20120003814
    Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.
    Type: Application
    Filed: June 16, 2011
    Publication date: January 5, 2012
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
  • Publication number: 20110159665
    Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 30, 2011
    Applicant: MEMC ELECTRONIC MATERIALS, INC.
    Inventors: Dale A. Witte, Jeffrey L. Libbert
  • Publication number: 20030170948
    Abstract: An apparatus for slicing semiconductor wafers from a single-crystal ingot includes a web of wire for slicing the ingot into wafers and a frame having a head for supporting the ingot during slicing. The apparatus further includes a controller and a temperature sensor disposed in the head and operable to send a signal to the controller indicating head temperature. The controller is operable to control temperature of a fluid directed to the head in response to the signal thereby to control the head temperature. Methods of slicing wafers are also disclosed.
    Type: Application
    Filed: February 28, 2003
    Publication date: September 11, 2003
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: Milind S. Bhagavat, Dale A. Witte, Steven L. Kimbel, David A. Sager, John W. Peyton
  • Patent number: 6200908
    Abstract: A process for reducing the waviness of a semiconductor wafer utilizing plasma assisted chemical etching is disclosed. The process includes measuring the surface profile at discrete points on one surface of the wafer independent from the apposing surface, computing a dwell time versus position map based on the measured surface profiles, and selectively removing material from each surface of the wafer by plasma assisted chemical etching to reduce the waviness of the wafer.
    Type: Grant
    Filed: August 4, 1999
    Date of Patent: March 13, 2001
    Assignee: MEMC Electronic Materials, Inc.
    Inventors: Roland Vandamme, Ankur Desai, Dale Witte, Yun-Biao Xin
  • Patent number: 6112738
    Abstract: Methods of slicing ingots of semiconductor material into wafers using a wire saw. The wire saw includes a wire that is movable in a forward direction and a reverse direction for slicing the ingots. The methods include defining an identification region of each wafer to be sliced from the ingots and aligning an alignment feature of the ingots in approximately the same position relative to the wire saw for each of the ingots. The identification region of the wafer is adapted for marking with an identification mark after slicing. The methods also include slicing the ingot into wafers with the wire saw. The slicing step includes moving the wire in the forward and reverse directions during slicing except when slicing in the identification region of each wafer and moving the wire only in the forward direction when slicing in the identification region of each wafer. In slicing the ingot into wafers, thickness variations relative to the size of the identification mark are reduced in the identification region.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: September 5, 2000
    Assignee: MEMC Electronics Materials, Inc.
    Inventors: Dale A. Witte, Tracy Ragan