Patents by Inventor Dale A. Witte
Dale A. Witte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180117690Abstract: A method for producing diamond grits for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated. The intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Omid Rezvanian, Larry Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
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Patent number: 9873159Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.Type: GrantFiled: December 30, 2015Date of Patent: January 23, 2018Assignee: Corner Star LimitedInventors: Omid Rezvanian, Larry Wayne Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
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Patent number: 9499920Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: GrantFiled: July 9, 2015Date of Patent: November 22, 2016Assignee: MEMC Singapore Pte. Ltd. (UEN200614794D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Publication number: 20160184909Abstract: A method for designing a diamond coated wire for use in a wafer slicing system includes adjusting an initial diamond size distribution until an intermediate diamond size distribution is generated, wherein the intermediate diamond size distribution has a corresponding simulated penetration thickness value less than or equal a predetermined penetration thickness value, and wherein penetration thickness is a parameter proportional to a depth of subsurface damage that would occur when slicing an ingot using a diamond coated wire having an associated diamond size distribution. The method may include adjusting the intermediate diamond size distribution until a final diamond size distribution is generated, wherein the final diamond size distribution has a maximum diamond grit size that is substantially equal to a predetermined maximum diamond grit size, and manufacturing the diamond coated wire such that the diamond coated wire has a plurality of diamond grits that fit the final diamond size distribution.Type: ApplicationFiled: December 30, 2015Publication date: June 30, 2016Inventors: Omid Rezvanian, Larry Wayne Shive, Rituraj Nandan, Dale A. Witte, Edward Calvin
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Publication number: 20150308011Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: ApplicationFiled: July 9, 2015Publication date: October 29, 2015Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Patent number: 9111745Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the alignment layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: GrantFiled: December 31, 2012Date of Patent: August 18, 2015Assignee: MEMC Singapore Pte., Ltd. (UEN200614794D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Patent number: 8900972Abstract: A method of producing rectangular seed bricks for use in semiconductor or solar manufacturing is disclosed. The method includes connecting an alignment layer to a top surface of a template, drawing alignment lines on the alignment layer to demarcate a plurality of nodes, connecting cylindrical rods to the alignment layer such that a center of each rod is aligned with a corresponding node, and slicing through the rods and the alignment layer with a wire web to produce rectangular seed bricks.Type: GrantFiled: November 19, 2012Date of Patent: December 2, 2014Assignee: MEMC Singapore Pte. Ltd.Inventors: Dale A. Witte, Jihong John Chen, Travis L. Hambach, Linda K. Swiney
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Patent number: 8859393Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.Type: GrantFiled: June 16, 2011Date of Patent: October 14, 2014Assignee: SunEdison Semiconductor LimitedInventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
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Patent number: 8845859Abstract: Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.Type: GrantFiled: March 12, 2012Date of Patent: September 30, 2014Assignee: SunEdison Semiconductor Limited (UEN201334164H)Inventors: Michael John Ries, Jeffrey L. Libbert, Dale A. Witte
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Publication number: 20140186486Abstract: An apparatus for producing rectangular seeds for use in semiconductor or solar material manufacturing includes a template having a top surface and parallel slots, and an adhesive layer connected to the top surface of the template. The adhesive layer includes alignment lines aligned with the parallel slots. The apparatus also includes quarter sections made of a semiconductor or solar material and connected to the alignment layer. An interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines. A wire web is adapted to slice through the interface of each quarter section to separate the rectangular seed portions from the curved wing portions to produce rectangular seeds.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Hayes, Tom Doane, Dale A. Witte, Linda K. Swiney, Travis Hambach
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Publication number: 20140182776Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the alignment layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Hayes, Tom Doane, Dale A. Witte, Linda K. Swiney, Travis Hambach
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Publication number: 20140137794Abstract: A method of preparing a directional solidification system (DSS) furnace for use in semiconductor or solar manufacturing includes slicing a plurality of cylindrical rods to produce a plurality of rectangular seed bricks, a plurality of corner portions, and a plurality of quarter sections, and cropping the plurality of rectangular seed bricks into a plurality of rectangular seeds.Type: ApplicationFiled: November 19, 2012Publication date: May 22, 2014Applicant: MEMC SINGAPORE, PTE. LTD (UEN200614797D)Inventors: Dale A. Witte, Jihong John Chen, Travis Hambach, Linda Swiney
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Publication number: 20140137395Abstract: A method of producing rectangular seed bricks for use in semiconductor or solar manufacturing is disclosed. The method includes connecting an alignment layer to a top surface of a template, drawing alignment lines on the alignment layer to demarcate a plurality of nodes, connecting cylindrical rods to the alignment layer such that a center of each rod is aligned with a corresponding node, and slicing through the rods and the alignment layer with a wire web to produce rectangular seed bricks.Type: ApplicationFiled: November 19, 2012Publication date: May 22, 2014Applicant: MEMC Singapore, Pte. Ltd (UEN200614797D)Inventors: Dale A. Witte, Jihong John Chen, Travis L. Hambach, Linda K. Swiney
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Publication number: 20130062020Abstract: Systems and methods are provided for mechanically cleaving a bonded wafer pair by controlling the rate of cleaving. This controlled rate of cleaving results in a reduction or elimination of non-uniform thickness variations in the cleaved surface of the resulting SOI wafer. One embodiment uses flexible chucks attached to the faces of the wafers and actuators attached to the flexible chucks to cleave the bonded wafer pair. Other embodiments also use rollers in contact with the surfaces to control the rate of cleaving.Type: ApplicationFiled: March 12, 2012Publication date: March 14, 2013Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Michael John Ries, Jeffrey L. Libbert, Dale A. Witte
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Patent number: 8367519Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.Type: GrantFiled: December 21, 2010Date of Patent: February 5, 2013Assignee: MEMC Electronic Materials, Inc.Inventors: Dale A. Witte, Jeffrey L. Libbert
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Publication number: 20120003814Abstract: Methods and systems are disclosed for performing a passivation process on a silicon-on-insulator wafer in a chamber in which the wafer is cleaved. A bonded wafer pair is cleaved within the chamber to form the silicon-on-insulator (SOI) wafer. A cleaved surface of the SOI wafer is then passivated in-situ by exposing the cleaved surface to a passivating substance. This exposure to a passivating substance results in the formation of a thin layer of oxide on the cleaved surface. The silicon-on-insulator wafer is then removed from the chamber. In other embodiments, the silicon-on-insulator wafer is first transferred to an adjoining chamber where the wafer is then passivated. The wafer is transferred to the adjoining chamber without exposing the wafer to the atmosphere outside the chambers.Type: ApplicationFiled: June 16, 2011Publication date: January 5, 2012Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Michael J. Ries, Dale A. Witte, Anca Stefanescu, Andrew M. Jones
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Publication number: 20110159665Abstract: This invention generally relates to a process for making a multi-layered crystalline structure. The process includes implanting ions into a donor structure, bonding the implanted donor structure to a second structure to form a bonded structure, cleaving the bonded structure, and removing any residual portion of the donor structure from the finished multi-layered crystalline structure.Type: ApplicationFiled: December 21, 2010Publication date: June 30, 2011Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Dale A. Witte, Jeffrey L. Libbert
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Publication number: 20030170948Abstract: An apparatus for slicing semiconductor wafers from a single-crystal ingot includes a web of wire for slicing the ingot into wafers and a frame having a head for supporting the ingot during slicing. The apparatus further includes a controller and a temperature sensor disposed in the head and operable to send a signal to the controller indicating head temperature. The controller is operable to control temperature of a fluid directed to the head in response to the signal thereby to control the head temperature. Methods of slicing wafers are also disclosed.Type: ApplicationFiled: February 28, 2003Publication date: September 11, 2003Applicant: MEMC Electronic Materials, Inc.Inventors: Milind S. Bhagavat, Dale A. Witte, Steven L. Kimbel, David A. Sager, John W. Peyton
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Patent number: 6200908Abstract: A process for reducing the waviness of a semiconductor wafer utilizing plasma assisted chemical etching is disclosed. The process includes measuring the surface profile at discrete points on one surface of the wafer independent from the apposing surface, computing a dwell time versus position map based on the measured surface profiles, and selectively removing material from each surface of the wafer by plasma assisted chemical etching to reduce the waviness of the wafer.Type: GrantFiled: August 4, 1999Date of Patent: March 13, 2001Assignee: MEMC Electronic Materials, Inc.Inventors: Roland Vandamme, Ankur Desai, Dale Witte, Yun-Biao Xin
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Patent number: 6112738Abstract: Methods of slicing ingots of semiconductor material into wafers using a wire saw. The wire saw includes a wire that is movable in a forward direction and a reverse direction for slicing the ingots. The methods include defining an identification region of each wafer to be sliced from the ingots and aligning an alignment feature of the ingots in approximately the same position relative to the wire saw for each of the ingots. The identification region of the wafer is adapted for marking with an identification mark after slicing. The methods also include slicing the ingot into wafers with the wire saw. The slicing step includes moving the wire in the forward and reverse directions during slicing except when slicing in the identification region of each wafer and moving the wire only in the forward direction when slicing in the identification region of each wafer. In slicing the ingot into wafers, thickness variations relative to the size of the identification mark are reduced in the identification region.Type: GrantFiled: April 2, 1999Date of Patent: September 5, 2000Assignee: MEMC Electronics Materials, Inc.Inventors: Dale A. Witte, Tracy Ragan