Patents by Inventor Dale C. Morris
Dale C. Morris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11221967Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.Type: GrantFiled: March 28, 2013Date of Patent: January 11, 2022Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Blaine D. Gaither, Dale C. Morris, Carey Huscroft, Russ W. Herrell
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Patent number: 11126372Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.Type: GrantFiled: November 11, 2019Date of Patent: September 21, 2021Assignee: Hewlett Packard Enterprise Development LPInventors: Russ W. Herrell, Gary Gostin, Gregg B Lesartre, Dale C. Morris
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Patent number: 10817361Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.Type: GrantFiled: May 7, 2018Date of Patent: October 27, 2020Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B Lesartre, Dale C Morris, Russ W Herrell, Blaine D Gaither
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Publication number: 20200081650Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.Type: ApplicationFiled: November 11, 2019Publication date: March 12, 2020Inventors: Russ W. Herrell, Gary Gostin, Gregg B. Lesartre, Dale C. Morris
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Patent number: 10474380Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.Type: GrantFiled: April 1, 2013Date of Patent: November 12, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Russ W. Herrell, Gary Gostin, Gregg B. Lesartre, Dale C. Morris
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Publication number: 20190340053Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.Type: ApplicationFiled: May 7, 2018Publication date: November 7, 2019Inventors: Gregg B. Lesartre, Dale C. Morris, Russ W. Herrell, Blaine D. Gaither
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Patent number: 10452498Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.Type: GrantFiled: June 28, 2013Date of Patent: October 22, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Dale C. Morris, Gary Gostin, Russ W. Herrell, Andrew R. Wheeler, Blaine D. Gaither
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Patent number: 9990244Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.Type: GrantFiled: January 30, 2013Date of Patent: June 5, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Greg B Lesartre, Dale C Morris, Russ W Herrell, Blaine D Gaither
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Patent number: 9927988Abstract: Examples disclosed herein provide moving a block of data between a source address and a target address. The examples disclose initiating a data move engine to move the block of data from the source address to the target address. Additionally, the examples disclose moving the block of data from the source address to the target address in a manner which allows a processor to concurrently access the block of data during the move.Type: GrantFiled: July 31, 2013Date of Patent: March 27, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Russ W. Herrell, Dale C. Morris
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Publication number: 20160170670Abstract: Examples disclosed herein provide moving a block of data between a source address and a target address. The examples disclose initiating a data move engine to move the block of data from the source address to the target address. Additionally, the examples disclose moving the block of data from the source address to the target address in a manner which allows a processor to concurrently access the block of data during the move.Type: ApplicationFiled: July 31, 2013Publication date: June 16, 2016Applicant: Hewlett-Packard Development Company, L.P.Inventors: Gregg B. LESARTRE, Russ W. HERRELL, Dale C. MORRIS
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Publication number: 20160147620Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.Type: ApplicationFiled: June 28, 2013Publication date: May 26, 2016Inventors: Gregg B. Lesartre, Dale C. Morris, Gary Gostin, Russ W. Herrell, Andrew R. Wheeler, Blaine D. Gaither
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Publication number: 20160113143Abstract: In some examples, a chassis contains a fabric module and a plurality node modules that are arranged in a plurality of rows. The fabric module is positioned in a space between a first row and a second row of the plurality of rows, and the fabric module is connected to at least two node modules of the plurality of node modules to provide communications connectivity between the at least two node modules, the chassis to accept longitudinal insertion in a longitudinal direction of the plurality of node modules and the fabric module, the fabric module being removable in the longitudinal direction from the chassis by moving the fabric module in the space between the first row and the second row without first removing the node modules in the plurality of rows.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Inventors: Martin Goldstein, Dale C. Morris, Michael R. Krause
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Publication number: 20160054944Abstract: A computing system is disclosed herein. The computing system includes a computing node and a remote memory node coupled to the computing node via a system fabric. The computing node includes a plurality of processors and a master memory controller. The master memory controller is external to the plurality of processors. The master memory controller routes requests corresponding to requests from the plurality of processors across the system fabric to the remote memory node and returns a response.Type: ApplicationFiled: April 1, 2013Publication date: February 25, 2016Inventors: Russ W. HERRELL, Gary GOSTIN, Gregg B. LESARTRE, Dale C. MORRIS
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Publication number: 20160041928Abstract: A system and method for addressing split modes of persistent memory are described herein. The system includes a non-volatile memory comprising regions of memory, each region comprising a range of memory address spaces. The system also includes a memory controller (MC) to control access to the non-volatile memory. The system further includes a device to track a mode of each region of memory and to define the mode of each region of memory. The mode is a functional use model.Type: ApplicationFiled: March 28, 2013Publication date: February 11, 2016Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Gregg B. Lesartre, Blaine D. Gaither, Dale C. Morris, Carey Huscroft, Russ W. Herrell
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Patent number: 9244736Abstract: Thinning operating systems can include monitoring a number of functionalities of an operating system, the number of functionalities of the operating system being provided by a number of computing components loaded thereon. Thinning operating systems can include automatically identifying an undesired functionality of the number of functionalities during runtime and removing from the operating system at least one of the number of computing components providing the undesired functionality as a result of the automatic identification to thin the OS.Type: GrantFiled: January 28, 2013Date of Patent: January 26, 2016Assignee: Hewlett Packard Enterprise Development LPInventors: Carey B. Huscroft, Benjamin D. Osecky, Aland B. Adams, Dale C. Morris, Stephen B. Lyle
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Patent number: 9223600Abstract: A data processor includes a redirection dynamic address redirection table (DART) for redirecting instruction fetches from an original memory location with an original address to a target memory location with a target address.Type: GrantFiled: May 7, 2007Date of Patent: December 29, 2015Assignee: Hewlett Packard Enterprise Development LPInventors: Jonathan K. Ross, Dale C. Morris, James M. Hull
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Publication number: 20150370721Abstract: The present disclosure provides techniques for mapping large shared address spaces in a computing system. A method includes creating a physical address map for each node in a computing system. Each physical address map maps the memory of a node. Each physical address map is copied to a single address map to form a global address map that maps all memory of the computing system. The global address map is shared with all nodes in the computing system.Type: ApplicationFiled: January 31, 2013Publication date: December 24, 2015Inventors: Dale C. Morris, Russ W. Herrell, Gary Gostin, Robert J. Brooks
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Patent number: 9219699Abstract: A chassis is configured to hold at least one horizontal row of node modules and a fabric module. The fabric module can be positioned above or below the row so that it can communicatively couple two or more node modules. Each of the node modules and the fabric modules can be inserted into and removed from the chassis longitudinally.Type: GrantFiled: September 15, 2010Date of Patent: December 22, 2015Assignee: Hewlett Packad Enterprise Development LPInventors: Martin Goldstein, Dale C. Morris, Michael R. Krause
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Publication number: 20150355961Abstract: A technique includes receiving an alert indicator in a distributed computer system that includes a plurality of computing nodes coupled together by cluster interconnection fabric. The alert indicator indicates detection of a fault in a first computing node of the plurality of computing nodes. The technique indicates regulating communication between the first computing node and at least one of the other computing nodes in response to the alert indicator to contain error propagation due to the fault within the first computing node.Type: ApplicationFiled: January 30, 2013Publication date: December 10, 2015Inventors: Greg B Lesartre, Dale C Morris, Russ W Herrell, Blaine D Gaither
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Publication number: 20140215468Abstract: Thinning operating systems can include monitoring a number of functionalities of an operating system, the number of functionalities of the operating system being provided by a number of computing components loaded thereon. Thinning operating systems can include automatically identifying an undesired functionality of the number of functionalities during runtime and removing from the operating system at least one of the number of computing components providing the undesired functionality as a result of the automatic identification to thin the OS.Type: ApplicationFiled: January 28, 2013Publication date: July 31, 2014Applicant: Hewlett-Packard Development Company, L.P.Inventors: Carey B. Huscroft, Benjamin D. Osecky, Aland B. Adams, Dale C. Morris, Stephen B. Lyle