Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: The magnetic field of an inductor is decreased by the presence of one or more single loop windings positioned in proximity to the inductor. The single loop windings have open circuits that are selectively closed to magnetically couple the single loop windings to the inductor. A switched inductor/varactor tuning circuit is formed by connecting a varactor to the inductor.

Abstract: The magnetic field of an inductor is decreased by the presence of one or more single loop windings positioned in proximity to the inductor. The single loop windings have open circuits that are selectively closed to magnetically couple the single loop windings to the inductor. A switched inductor/varactor tuning circuit is formed by connecting a varactor to the inductor.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modem RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A transistor array including a plurality of transistors. Each transistor includes an emitter. An emitter region contact overlies each emitter region. At least one base region underlies each emitter region and is common to a plurality of transistors in the array. At least one base contact overlies the at least one base region and is associated with each transistor. A plurality of the base contacts are common to at least two transistors in the array. At least one collector reach through is associated with each transistor. A collector reach through contact overlies each collector reach through. A buried layer subcollector region of electrically conducting material electrically connects the collector reach through region to the collector pedestal region of each transistor.

Abstract: A low noise, high frequency solid state diode is provided from a plurality of unit diode cells which are interconnected in parallel. Each of the unit diode cells forms an element of an array having rows and columns of unit diode cells. The diode cells include a base region of polysilicon, forming an anode, and an active cathode region which forms a diode junction with the anode. A plurality of overlapping subcollector regions interconnect the cathode regions, to provide a single, continuous collector for the diode arrays. The base region has a minimum perimeter to area ratio which reduces the resistance of each active diode region. A plurality of cathode contacts are connected to the subcollector through a respective reach region of highly doped semiconductor material. One or more metalization layers connect the cathode regions together, and the anodes of the base regions together. By controlling the size and shape of the base region of polysilicon, the series resistance of the resulting diode is minimized.

Abstract: A radio frequency power amplifier for a battery powered handset unit of a wireless communications system having a low power signal amplification path and a high power signal amplification path. Logic and biasing means within the handset select between the low power signal path and the high power signal depending upon the handset being within or outside a prescribed distance from a base station. In this way, the signals received at the base station from the handset are at the required power level.

Abstract: This current switch driving circuitry, particularly for, but not necessarily limited to, inductive device current switching, comprises a pair of output transistors constituting a driving transistor for turning ON a subsequent switching transistor and a current sinking transistor for turning OFF that switching transistor with circuit provisions for maintaining the two transistors in a low power consuming standby state. A pair of receiver circuits are arranged for applying ON and OFF logical signals individually to the two transistors by way of intermediate circuitry having current multiplying circuitry for deriving the necessary driving power with a minimum of power consumed.