Patents by Inventor Dan M. Mosher
Dan M. Mosher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7888196Abstract: A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness<the second thickness. A substrate having a semiconducting surface is provided. A pad dielectric layer having a thickness?the second thickness is formed on the semiconductor surface including over the second regions, wherein the pad dielectric layer provides at least a portion of the second thickness for the second gate dielectric. A hard mask layer is formed on the semiconductor surface including over the second regions. A plurality of trench isolation regions are formed by etching through the pad dielectric layer and a portion of the semiconductor surface.Type: GrantFiled: December 29, 2008Date of Patent: February 15, 2011Assignee: Texas Instruments IncorporatedInventors: Seetharaman Sridhar, Sameer Pendharkar, Dan M. Mosher
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Publication number: 20100163998Abstract: A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness<the second thickness. A substrate having a semiconducting surface is provided. A pad dielectric layer having a thickness?the second thickness is formed on the semiconductor surface including over the second regions, wherein the pad dielectric layer provides at least a portion of the second thickness for the second gate dielectric. A hard mask layer is formed on the semiconductor surface including over the second regions. A plurality of trench isolation regions are formed by etching through the pad dielectric layer and a portion of the semiconductor surface.Type: ApplicationFiled: December 29, 2008Publication date: July 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Seetharaman Sridhar, Sameer Pendharkar, Dan M. Mosher
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Patent number: 6804095Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.Type: GrantFiled: July 14, 2003Date of Patent: October 12, 2004Assignee: Texas Instruments IncorporatedInventors: Keith E. Kunz, Charvaka Duvvury, Dan M. Mosher
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Publication number: 20040027745Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.Type: ApplicationFiled: July 14, 2003Publication date: February 12, 2004Inventors: Keith E. Kunz, Charvaka Duvvury, Dan M. Mosher
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Patent number: 6624487Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.Type: GrantFiled: June 5, 2002Date of Patent: September 23, 2003Assignee: Texas Instruments IncorporatedInventors: Keith E. Kunz, Charvaka Duvvury, Dan M. Mosher
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Patent number: 6620692Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (782) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (781) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (71a) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.Type: GrantFiled: April 26, 2002Date of Patent: September 16, 2003Assignee: Texas Instruments IncorporatedInventors: David B. Scott, Dan M. Mosher
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Publication number: 20030127694Abstract: An integrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50),(140) and drain regions (55),(145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70),(80) serve as the drain extension regions of the transistors.Type: ApplicationFiled: December 13, 2002Publication date: July 10, 2003Inventors: Alec Morton, Taylor Efland, Chin-Yu Tsai, Jozef C. Mitros, Dan M. Mosher, Sam Shichijo, Keith Kunz
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Publication number: 20030102492Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (722) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (721) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (72a1) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.Type: ApplicationFiled: April 26, 2002Publication date: June 5, 2003Inventors: David B. Scott, Dan M. Mosher
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Patent number: 6548874Abstract: An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.Type: GrantFiled: September 26, 2000Date of Patent: April 15, 2003Assignee: Texas Instruments IncorporatedInventors: Alec Morton, Taylor Efland, Chin-yu Tsai, Jozef C. Mitros, Dan M. Mosher, Sam Shichijo, Keith Kunz
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Patent number: 6531355Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.Type: GrantFiled: July 1, 1999Date of Patent: March 11, 2003Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Taylor R. Efland
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Patent number: 6521946Abstract: A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a semiconductor material and defining a channel area (66) in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source (S2) comprising a first doped region (581) of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain (D2). The drain comprises a first well (641) adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion (68). The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well.Type: GrantFiled: November 30, 2001Date of Patent: February 18, 2003Assignee: Texas Instruments IncorporatedInventor: Dan M. Mosher
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Patent number: 6483149Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.Type: GrantFiled: May 14, 1997Date of Patent: November 19, 2002Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Taylor R. Efland
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Publication number: 20020074606Abstract: A semiconductor device comprising a first transistor (40) and a second transistor (100), both formed in a semiconductor substrate (50). The first transistor comprises a gate conductor (56) and a gate insulator (54) separating the gate conductor from a semiconductor material and defining a channel area (66) in the semiconductor material opposite from the gate conductor. The first transistor further comprises a source (S2) comprising a first doped region (581) of a first conductivity type and adjacent the channel area. Further, the first transistor comprises a drain (D2). The drain comprises a first well (641) adjacent the channel area and having a first concentration of the first conductivity type and a first doped region portion and a second doped portion (68). The first doped portion has a second concentration of the first conductivity type. The second concentration is greater than the first concentration and the first doped region portion has a common interface with the first well.Type: ApplicationFiled: November 30, 2001Publication date: June 20, 2002Inventor: Dan M. Mosher
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Publication number: 20020063263Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (722) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (721) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (72a1) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.Type: ApplicationFiled: November 30, 2001Publication date: May 30, 2002Inventors: David B. Scott, Dan M. Mosher
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Publication number: 20010053581Abstract: A RESURF LDMOS transistor (64) includes a RESURF region (42) that is self-aligned to a LOCOS field oxide region (44). The self-alignment produces a stable breakdown voltage BVdss by eliminating degradation associated with geometric misalignment and process tolerance variation.Type: ApplicationFiled: July 1, 1999Publication date: December 20, 2001Inventors: DAN M. MOSHER, TAYLOR R. EFLAND
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Patent number: 6211552Abstract: A RESURF LDMOS transistor (32) has a drain region including a first region (24) and a deep drain buffer region (34) surrounding the first region. The first region is more heavily doped than the deep drain buffer region. The deep drain buffer region improves the robustness of the transistor.Type: GrantFiled: May 27, 1999Date of Patent: April 3, 2001Assignee: Texas Instruments IncorporatedInventors: Taylor R. Efland, Sameer Pendharkar, Dan M. Mosher, Peter Chia-cu Mei
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Patent number: 5256582Abstract: The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for fabricating a high power/logic complementary bipolar/MOS/DMOS (CBiCMOS) integrated circuit. The process steps for fabricating the novel integrated circuit combines on the same substrate complementary high power, logic/analog bipolar transistors with complementary MOSGVm devices and DMOSFET devices. The present invention optimizes the characteristics of these different transistors in a single process flow. The present high power/logic CBiCMOS multiepitaxial process results in device structures having distinct technical advantages over prior art processes and structures heretofore known.Type: GrantFiled: November 27, 1991Date of Patent: October 26, 1993Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton, Bob Todd
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Patent number: 5181095Abstract: An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground region extending from the substrate to the third epitaxial layer in a first tank region and extending through the first and second epitaxial layers. A power bipolar transistor is formed in the first tank region. P isolation areas extending from the surface of the third epitaxial layer to the P ground region isolate the bipolar transistor from other tank region on the same substrate in which N and P channel MOSFETS are formed.Type: GrantFiled: April 19, 1991Date of Patent: January 19, 1993Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Larry Latham, Bob Todd, Cornelia H. Blanton, Joe R. Trogolo, David R. Cotton
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Patent number: 5153697Abstract: An integrated circuit is formed on an N-type semiconductor wafer having a first N-type epitaxial layer on the substrate, a P-type epitaxial layer over the first N-type epitaxial layer, and a second N-type epitaxial layer over the P-type epitaxial layer. There are also a plurality of sets of P-type isolation regions separating the P-type epitaxial region and the surface of the second N-type epitaxial region into epitaxial tank regions for formation of bipolar and CMOS devices, combining high power, low power, logic, switching, analog, high current, low current, digital, and linear bipolar transistors along with CMOS transistors. The characteristics of the different type of devices are combined into a single process flow.Type: GrantFiled: May 6, 1991Date of Patent: October 6, 1992Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton
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Patent number: 5034337Abstract: A process of fabricating semiconductor devices involving plural epitaxial layer growth steps.Type: GrantFiled: August 29, 1990Date of Patent: July 23, 1991Assignee: Texas Instruments IncorporatedInventors: Dan M. Mosher, Cornelia H. Blanton, Joe R. Trogolo, Larry Latham, David R. Cotton