Patents by Inventor Daniel A. Uriarte

Daniel A. Uriarte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • plants having a mutant polynucleotide encoding the large subunit of mutated acetohydroxyacid synthase protein and increased resistance to herbicides
    Patent number: 11963498
    Abstract: A sorghum seed comprising in its genome at least one polynucleotide encoding a polypeptide having an alanine to tyrosine substitution at position 93 of the sorghum AHAS protein large subunit. The plant has increased resistance to one or more herbicides, for example from the imidazolinone group, as compared to wild-type sorghum plants. The sorghum plant may comprise in its genome, one, two, three or more copies of a polynucleotide encoding a mutated large subunit of sorghum AHAS or a sorghum AHAS polypeptide of the invention. In this context, the sorghum plant may be tolerant to any herbicide capable of inhibiting AHAS enzyme activity. For example, the sorghum plant may be tolerant to herbicides of the imidazolinones type, such as imazethapyr, imazapir, and imazapic or to herbicides of the sulfonylurea group.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: April 23, 2024
    Assignee: Advanta Holdings BV
    Inventors: Vicente Trucillo Uriarte, Andrés Daniel Zambelli, Marcos Kaspar, Pedro Alejandro Pardo
  • CMOS device structure with improved PFET gate electrode
    Patent number: 6838695
    Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.
    Type: Grant
    Filed: November 25, 2002
    Date of Patent: January 4, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Ashima B. Chakravarti, Kevin K. Chan, Daniel A. Uriarte
  • CMOS device structure with improved PFET gate electrode
    Publication number: 20040099860
    Abstract: A semiconductor device structure includes a substrate, a dielectric layer disposed on the substrate, first and second stacks disposed on the dielectric layer. The first stack includes a first silicon layer disposed on the dielectric layer, a silicon germanium layer disposed on the first silicon layer, a second silicon layer disposed on the silicon germanium layer, and a third silicon layer disposed on the second silicon layer. The second stack includes a first silicon layer disposed on the dielectric layer, and a second silicon layer disposed on the first silicon layer. Alternatively, the silicon germanium layer includes Boron.
    Type: Application
    Filed: November 25, 2002
    Publication date: May 27, 2004
    Applicant: International Business Machines Corporation
    Inventors: Bruce B. Doris, Ashima B. Chakravarti, Kevin K. Chan, Daniel A. Uriarte