Patents by Inventor Daniel B. Aubertine
Daniel B. Aubertine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9653584Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.Type: GrantFiled: December 23, 2013Date of Patent: May 16, 2017Assignee: Intel CorporationInventors: Glenn A. Glass, Anand S. Murthy, Daniel B. Aubertine, Subhash M. Joshi
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Publication number: 20170133376Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).Type: ApplicationFiled: March 24, 2014Publication date: May 11, 2017Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, ANAND S. MURTHY, DANIEL B. AUBERTINE, SUBHASH M. JOSHI
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Publication number: 20160308032Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.Type: ApplicationFiled: December 23, 2013Publication date: October 20, 2016Inventors: Glenn A. GLASS, Anand s. MURTHY, Daniel B. AUBERTINE, Subhash M. JOSHI
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Publication number: 20160260802Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: ApplicationFiled: May 16, 2016Publication date: September 8, 2016Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, KELIN J. KUHN, SEIYON KIM, ANAND S. MURTHY, DANIEL B. AUBERTINE
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Patent number: 9343559Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: GrantFiled: April 20, 2015Date of Patent: May 17, 2016Assignee: INTEL CORPORATIONInventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
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Publication number: 20160079423Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Applicant: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20160071934Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.Type: ApplicationFiled: November 9, 2015Publication date: March 10, 2016Applicant: Intel CorporationInventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
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Patent number: 9231076Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: December 24, 2014Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 9184294Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.Type: GrantFiled: September 24, 2014Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
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Publication number: 20150228772Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Applicant: INTEL CORPORATIONInventors: GLENN A. GLASS, KELIN J. KUHN, SEIYON KIM, ANAND S. MURTHY, DANIEL B. AUBERTINE
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Patent number: 9076814Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: June 6, 2014Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20150155384Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: December 24, 2014Publication date: June 4, 2015Applicant: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20150115216Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.Type: ApplicationFiled: January 7, 2015Publication date: April 30, 2015Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
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Patent number: 9012284Abstract: Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.Type: GrantFiled: July 27, 2012Date of Patent: April 21, 2015Assignee: Intel CorporationInventors: Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Anand S. Murthy, Daniel B. Aubertine
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Patent number: 8957476Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.Type: GrantFiled: December 20, 2012Date of Patent: February 17, 2015Assignee: Intel CorporationInventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea
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Publication number: 20150008484Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.Type: ApplicationFiled: September 24, 2014Publication date: January 8, 2015Applicant: INTEL CORPORATIONInventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
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Patent number: 8847281Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.Type: GrantFiled: July 27, 2012Date of Patent: September 30, 2014Assignee: Intel CorporationInventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
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Publication number: 20140284626Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: June 6, 2014Publication date: September 25, 2014Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 8779477Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: August 14, 2008Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20140175543Abstract: Embodiments of the present disclosure provide techniques and configurations associated with conversion of thin transistor elements from silicon (Si) to silicon germanium (SiGe). In one embodiment, a method includes providing a semiconductor substrate having a channel body of a transistor device disposed on the semiconductor substrate, the channel body comprising silicon, forming a cladding layer comprising germanium on the channel body, and annealing the channel body to cause the germanium to diffuse into the channel body. Other embodiments may be described and/or claimed.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Stephen M. Cea