Abstract: A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A metal layer fills a first portion of the set of features and is disposed over the adhesion promoting layer. A ruthenium layer is disposed over the metal layer. A cobalt layer is disposed over the ruthenium layer fills a second portion of the set of features. The cobalt layer is formed using a physical vapor deposition process.

Abstract: An integrated circuit device having a substrate including a dielectric layer is patterned with a set of conductive line trenches. Each conductive line trench of the conductive line pattern having parallel vertical sidewalls and a horizontal bottom. A metal fills the set of conductive line trenches, wherein the metal fill is created by an anneal and reflow process. A liner which is an alloy of the metal and a selected element formed at interfaces of the metal layer and a surface of the dielectric, created simultaneously with the metal fill by the anneal and reflow process.

Abstract: A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The anode and cathode regions are comprised of a large grained copper layer and an aspect ratio reducing layer, and the fuse element is comprised of a fine grained copper structure.

Abstract: A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. The set of features have a first dimension. An adhesion promoting layer disposed over the patterned dielectric is deposited. A ruthenium layer disposed over the adhesion promoting layer is deposited. A cobalt layer is deposited over the ruthenium layer. A high temperature thermal anneal is performed which creates a ruthenium cobalt alloy layer to cover surfaces of the set of features. A metal layer is deposited disposed over the ruthenium cobalt alloy layer to form a set of metal conductor structures. In another aspect of the invention, a device is created using the method.

Abstract: A semiconductor structure. The semiconductor structure includes two or more pillar structures disposed over a top surface of a substrate. The semiconductor structure further includes two or more contacts to the two or more pillar structures. The semiconductor structure further includes an insulator disposed between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures.

Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

Abstract: An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium cobalt alloy layer is disposed over the adhesion promoting layer. A metal layer is disposed over the ruthenium cobalt alloy layer filling the set of features.

Abstract: A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion.

Abstract: A method of forming a semiconductor structure includes forming two or more pillar structures over a top surface of a substrate. The method also includes forming two or more contacts to the two or more pillar structures. The method further includes forming an insulator between the two or more pillar structures and the two or more contacts. The two or more contacts are self-aligned to the two or more pillar structures by forming the insulator via conformal deposition and etching the insulator selective to a spin-on material formed over the insulator between the two or more pillar structures.

Abstract: A semiconductor structure containing at least two metal resistor structures having different amounts of nitrogen on the resistor surface is provided. The resulted resistances (and hence resistivity) of the two metal resistors can be either the same or different. The semiconductor structure may include a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first metal layer portion and a first nitridized metal surface layer having a first nitrogen content. The semiconductor structure further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second metal layer portion and a second nitridized metal surface layer having a second nitrogen content that differs from the first nitrogen content.

Abstract: In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions. The trench is provided in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions. The trench is filled with copper. An annealing step converts the copper to create a large grained copper structure in the anode and cathode regions and a fine grained copper structure in the fuse element. Another aspect of the invention is an e-Fuse device which includes an anode region, a cathode region and a fuse element which interconnects the anode and cathode regions in a dielectric material on a first surface of a substrate. The fuse element has a smaller cross section and a higher aspect ratio than the anode and cathode regions.

Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.

Abstract: The present application provides planar and stacked resistor structures that are embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material or electrical conducting resistive materials of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, a doped metallic insulator layer is formed atop a substrate. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer. The remaining doped metallic insulator layer and the electrical conducting resistive material layer are then patterned to provide the resistor structure.

Abstract: A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

Abstract: The present application provides a 3D resistor structure that is embedded within an interconnect dielectric material in which the resistivity of an electrical conducting resistive material of the 3D resistor structure can be tuned to a desired resistivity during the manufacturing of the 3D resistor structure. Notably, a patterned doped metallic insulator is formed straddling over an dielectric pillar. A controlled surface treatment process is then performed to an upper portion of the patterned doped metallic insulator to convert the upper portion of the patterned doped metallic insulator into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining patterned doped metallic insulator and the electrical conducting resistive material.

Abstract: A semiconductor structure is provided that includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal portion, and a first dielectric capping layer portion. The semiconductor structure of the present application further includes a second metal resistor structure located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content that differs from the first nitrogen content, a second metal portion, and a second dielectric capping layer portion.

Abstract: A resistor structure is provided that contains curved resistor elements. The resistor structure is embedded within an interconnect dielectric material and the resistivity of an electrical conducting resistive material of the resistor structure can be tuned to a desired resistivity during the manufacturing of the resistor structure. Notably, an electrical conducting metallic structure having a concave outermost surface is provided in a dielectric material layer. A doped metallic insulator layer is formed on the concave outermost surface of the metallic structure. A controlled surface treatment process is then performed to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material. An interconnect dielectric material can then be formed to embed the entirety of the remaining doped metallic insulator layer and the electrical conducting resistive material.

Abstract: A semiconductor structure containing at least two metal resistor structures having different resistivities is provided and includes a first metal resistor structure located on a portion of a dielectric-containing substrate. The first metal resistor structure includes, from bottom to top, a first nitridized dielectric surface layer portion having a first nitrogen content, a first metal layer portion and a first nitridized metal surface layer. A second metal resistor structure is located on a second portion of the dielectric-containing substrate and spaced apart from the first metal resistor structure. The second metal resistor structure includes, from bottom to top, a second nitridized dielectric surface layer portion having a second nitrogen content, a second metal layer portion and a second nitridized metal surface layer. The second nitrogen content of the second nitridized dielectric surface layer portion differs from the first nitrogen content of the first nitridized dielectric surface layer portion.