Abstract: A Central Processing Unit provides programmable variation of the operand width for processor operations. The operands are formed with one or more N-bit segments. The CPU includes an arithmetic logic unit (ALU) which is adapted to operate serially on one N-bit segment of the operand at a time beginning with the least significant segment and repeating the operation on the remaining segments according to their order of significance. The number of repetitions of an ALU operation is controlled by a code stored in an op-code extension register (OER). The code in the OER can be changed by means of an instruction for transferring a new code to OER.

Abstract: A Central Processing Unit (CPU) provides programmable autoloading of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoloading status of each memory pointer register. Whether or not a particular memory pointer register is loaded at the end of an instruction cycle with an operand address carried by the current instruction depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the OER can be changed by means of an instruction for transferring a new code to OER. A CPU architecture having an OER permits software specification of autoloading without significantly increasing the number of op-codes required to define the instruction set. Fewer op-codes generally permit shorter instructions.

Abstract: A Central Processing Unit (CPU) provides programmable autoincrementing of memory pointer registers. The CPU includes an op-code extension register (OER) to store a code specifying the autoincrementing status of each memory pointer register. Whether or not a particular memory pointer register containing the address of an operand used in the current operation is automatically incremented at the end of an instruction cycle to contain the address of an operand required for the next operation depends on the binary state of a particular bit position in the OER corresponding to the particular memory pointer register. The contents of the op-code extension register can be changed by means of an instruction for transferring a new code to OER.