Patents by Inventor Daniel F. Cutter

Daniel F. Cutter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10268412
    Abstract: A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 23, 2019
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel F. Cutter
  • Patent number: 10224959
    Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: March 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Daniel F. Cutter, Wajdi K. Feghali
  • Patent number: 10224956
    Abstract: In one embodiment, an apparatus comprises a first compression engine to receive a first compressed data block from a second compression engine that is to generate the first compressed data block by compressing a first plurality of repeated instances of data that each have a length greater than or equal to a first length. The first compression engine is further to compress a second plurality of repeated instances of data of the first compressed data block that each have a length greater than or equal to a second length, the second length being shorter than the first length, wherein each compressed repeated instance of the first and second pluralities of repeated instances comprises a location and length of a data instance that is repeated. The apparatus further comprises a memory buffer to store the compressed first and second plurality of repeated instances of data.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 5, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Daniel F. Cutter
  • Patent number: 10191684
    Abstract: Technologies for flexibly compressing data include a computing device having an accelerator complex that is to receive a compression job request and schedule the compression job request for one or more hardware compression resources of the accelerator complex. The accelerator complex is further to perform the compression job request with the one or more hardware compression resources in response to scheduling the compression job request and to communicate uncompressed data and compressed data with an I/O subsystem of the computing device in response to performing the compression job request. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Daniel F. Cutter, Wajdi K. Feghali
  • Patent number: 10140046
    Abstract: A processing system is provided that includes a memory for storing an input bit stream and a processing logic, operatively coupled to the memory, to generate a first score based on: a first set of matching data related to a match between a first bit subsequence and a candidate bit subsequence within the input bit stream, and a first distance of the candidate bit subsequence from the first set of matching data. A second score is generated based on a second set of matching data related to a match between a second bit subsequence and the candidate bit subsequence, and a second distance of the candidate bit subsequence from the second set of matching data. A code to replace the first or second bit subsequence in an output bit stream is identified. Selection of the one of the bit subsequences to replace is based on a comparison of the scores.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 27, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Patent number: 10120609
    Abstract: A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: November 6, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Daniel F. Cutter
  • Patent number: 10116327
    Abstract: Technologies for compressing data with multiple hash tables include a compute device. The compute device is to produce, for each of multiple string prefixes of different string prefix sizes, an associated hash. Each string prefix defines a set of consecutive symbols in a string that starts at a present position in an input stream of symbols. The compute device is also to write, to a different hash table for each string prefix size, a pointer to the present position in association with the associated hash. Each hash is usable as an index into the associated hash table to provide the present position of the string.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: October 30, 2018
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Publication number: 20180310012
    Abstract: Methods and apparatus are described by which data is compressed using semi-dynamic Huffman code generation. Embodiments generate symbol statistics over a portion of data. The symbol statistics are expanded to include all possible literals that could appear within the data. Any literal or reference added to the statistics may be given a frequency of one. The statistics are used to generate a semi-dynamic Huffman code. The entire data is then compressed using the semi-dynamic Huffman code.
    Type: Application
    Filed: April 25, 2017
    Publication date: October 25, 2018
    Inventors: Gregory B. Tucker, James D. Guilford, Daniel F. Cutter, Vinodh Gopal, Wajdi K. Feghali
  • Patent number: 10102215
    Abstract: A processor includes a memory hierarchy, buffer, and a compression module. The compression module includes logic to evaluate a stream of data to be compressed according to a compression scheme, selectively modify a format of the compression scheme based upon a number of literals received, compress a sequence of the data to produce the output data sequence, and send the output data sequence to the memory hierarchy.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: James D. Guilford, Vinodh Gopal, Gilbert M. Wolrich, Daniel F. Cutter
  • Patent number: 10097201
    Abstract: Methods and apparatus are described by for compressing data using LZ77 compression. Embodiments determine an initial run from input data. The initial run includes repeating data at a first location and has a first length. A hash chain is updated with a proper set of hashes from prefixes from the initial run. A first search engine determines a second run that includes the repeating data at a second location. The second run has a second length less than the first length. A first matching location is determined within the input data having the repeating data using the hash chain and the second run. The first matching location is the first location. The first matching location, the second location, and the second length are written to an output buffer. The output buffer includes a compressed version of the input data.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Daniel F. Cutter
  • Publication number: 20180287630
    Abstract: Techniques and apparatus for verification of compressed data are described. In one embodiment, for example an apparatus to provide verification of compressed data may include at least one memory and logic, at least a portion of comprised in hardware coupled to the at least one memory, the logic to access compressed data, access compression information associated with the compressed data, decompress at least a portion of the compressed data to generate decompressed data, and verify the compressed data via a comparison of the decompressed data with the compression information. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2018
    Publication date: October 4, 2018
    Applicant: INTEL CORPORATION
    Inventors: VINODH GOPAL, JAMES D. GUILFORD, KIRK S. YAP, DANIEL F. CUTTER, WAJDI K. FEGHALI
  • Patent number: 10033404
    Abstract: Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at a present position and a predefined number of symbols after the present position in an input stream, determine whether the symbol at the present position is part of a run, obtain, from a hash table, a chain of pointers to previous positions in the input stream associated with the hash, determine, as a function of whether the symbol is part of a run and to identify a matched string, a number of strings referenced by the chain of pointers to compare to a string associated with the present position in the input stream, and output, in response to an identification of a matched string, a reference to the matched string in a set of compressed output data.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Daniel F. Cutter, Vinodh Gopal, James D. Guilford
  • Publication number: 20180189202
    Abstract: An apparatus is described. The apparatus includes a main memory controller having a point-to-point link interface to couple to a point-to-point link. The point-to-point link is to transport system memory traffic between said main memory controller and a main memory. The main memory controller includes at least one of compression logic circuitry to compress write information prior to being transmitted over the link; decompression logic circuitry to decompress read information after being received from the link.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Kirk S. YAP, Daniel F. CUTTER, Vinodh GOPAL
  • Publication number: 20180183900
    Abstract: In an embodiment, a processor comprises a plurality of processing cores and a compression accelerator to compress an input stream comprising a first data block and a second data block. The compression accelerator comprises a first compression engine to compress the first data block; and a second compression engine to update state data for the second compression engine using a sub-portion of the first data block; and after an update of the state data for the second compression engine using the sub-portion of the first data block, compress a second data block using the updated state data for the second compression engine. Other embodiments are described and claimed.
    Type: Application
    Filed: December 26, 2016
    Publication date: June 28, 2018
    Inventors: JAMES D. GUILFORD, VINODH GOPAL, DANIEL F. CUTTER
  • Patent number: 9996487
    Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jose S. Niell, Daniel F. Cutter, Stephen J. Robinson, Mukesh K. Patel
  • Publication number: 20180159551
    Abstract: In one embodiment, an apparatus comprises a first compression engine to receive a first compressed data block from a second compression engine that is to generate the first compressed data block by compressing a first plurality of repeated instances of data that each have a length greater than or equal to a first length. The first compression engine is further to compress a second plurality of repeated instances of data of the first compressed data block that each have a length greater than or equal to a second length, the second length being shorter than the first length, wherein each compressed repeated instance of the first and second pluralities of repeated instances comprises a location and length of a data instance that is repeated. The apparatus further comprises a memory buffer to store the compressed first and second plurality of repeated instances of data.
    Type: Application
    Filed: November 17, 2017
    Publication date: June 7, 2018
    Applicant: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Daniel F. Cutter
  • Publication number: 20180150471
    Abstract: Technologies for database acceleration include a computing device having a database accelerator. The database accelerator performs a decompress operation on one or more compressed elements of a compressed database to generate one or more decompressed elements. After decompression of the compressed elements, the database accelerator prepares the one or more decompressed elements to generate one or more prepared elements to be processed by an accelerated filter. The database accelerator then performs the accelerated filter on the one or more prepared elements to generate one or more output elements. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Simon N. Peffers, Daniel F. Cutter
  • Publication number: 20180152201
    Abstract: Technologies for flexibly compressing data include a computing device having an accelerator complex that is to receive a compression job request and schedule the compression job request for one or more hardware compression resources of the accelerator complex. The accelerator complex is further to perform the compression job request with the one or more hardware compression resources in response to scheduling the compression job request and to communicate uncompressed data and compressed data with an I/O subsystem of the computing device in response to performing the compression job request. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: Vinodh Gopal, James D. Guilford, Kirk S. Yap, Daniel F. Cutter, Wajdi K. Feghali
  • Publication number: 20180152200
    Abstract: A compute device to generate deterministic compressed streams receives a current string to be matched to one or more prior instances of the current string, the current string being located within an input buffer and the one or more prior instances located within a history buffer. The compute device identifies a limited subset of index memory designated for storing pointers to the prior instances, identifying a reserved slop region in the index memory, and compares the current string to a prior instance, locating the at least one prior instance using at least one pointer to the at least one prior instance. The at least one pointer is stored within the limited subset of the index memory, and the compute device also prohibits use of any pointers stored in the reserved slop region of the index memory. Other embodiments are described and claimed.
    Type: Application
    Filed: September 29, 2017
    Publication date: May 31, 2018
    Inventors: James D. Guilford, Vinodh Gopal, Daniel F. Cutter
  • Patent number: 9954552
    Abstract: Technologies for performing low-latency decompression include a managed node to parse, in response to a determination that a read tree descriptor does not match a cached tree descriptor, the read tree descriptor to construct one or more tables indicative of codes in compressed data. Each code corresponds to a different symbol. The managed node is further to decompress the compressed data with the one or more tables and store the one or more tables in association with the read tree descriptor in a cache memory for subsequent use.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, Daniel F. Cutter, James D. Guilford, Kirk S. Yap