Abstract: Integrated table motion includes a computer-assisted device. The computer-assisted device includes articulating means; means for receiving, via a means for communicatively coupling the computer-assisted device with a table means, a table movement request from a table command means, the table means being separate from the computer-assisted device; means for determining whether the table movement request should be allowed; and means for allowing the table means to perform the table movement request based on determining that the table movement request should be allowed.

Abstract: A delay circuit is coupled to a memory device. At least a portion of the delay circuit is disposed in one or more memory banks on one or more memory chips of the memory device. The delay circuit is configured to calibrate an asynchronous signal received at each of the one or more memory banks so that the calibrated asynchronous signal has a common timing relationship with a respective internal command signal received at the corresponding memory bank for all of the one or more memory banks on the memory device. The calibrated asynchronous signals are used in various internal test operations to improve testing accuracy.

Abstract: A nuclear reactor includes a heat exchanger that transfers thermal energy from a primary reactor coolant to a secondary coolant. The heat exchanger is formed with a hot flow channel, a cold flow channel, and a porous layer between the hot flow channel and the cold flow channel. The porous layer may be thermally insulative to reduce the efficiency of thermal energy transfer from the hot flow channel to the cold flow channel. The porous layer may have a control gas passed therethrough that can be tailored to control the thermal energy transfer through the porous layer. The control gas can be tested for leakage within the heat exchanger. The control gas may also be used to sequester fission or activation products.

Abstract: An apparatus includes a TM control circuit that is configured to receive address information corresponding to a TM function and compare the address information with an authorized TM list stored in a memory of the apparatus to determine if there is a match. If there is a match, a latch load signal pulse is output. A TM latch circuit programs one or more latches based on the address information and based on the latch load signal pulse. The TM latch circuit decodes information in the one or more latches and, based on the decoded information, outputs a test mode signal to turn on test mode operations in circuits associated with the TM function. The apparatus includes a plurality of TM functions for testing various features of the apparatus and the authorized TM list identifies which of the plurality of TM functions has been authorized for customer use.

Abstract: An electronic device includes multiple memory elements including multiple redundant memory elements. The electronic device also includes repair circuitry configured to remap data to the multiple memory elements when a failure occurs. The repair circuitry includes multiple fuse latches configured to implement the remapping. The repair circuitry also includes latch testing circuitry configured to test functionality of the multiple fuse latches. The latch testing circuitry includes selection circuitry configured to enable selection of a first set of fuse latches of the multiple fuse latches for a test separate from a second set of fuse latches of the multiple fuse latches that are unselected by the selection circuitry.

Abstract: A system includes a first simulated processing system having a first clock and a second simulated processing system having a second clock. The first and second processing systems may operate asynchronously. A synchronization bridge may coordinate executing of the first synchronized processing system and the second synchronized processing system to synchronize the time of execution of the first and second simulated processing systems and messaging between the first and second processing systems. The first and second processing systems may be simulated processing systems.

Abstract: A system includes a first simulated processing system having a first clock and a second simulated processing system having a second clock. The first and second processing systems may operate asynchronously. A synchronization bridge may coordinate executing of the first synchronized processing system and the second synchronized processing system to synchronize the time of execution of the first and second simulated processing systems and messaging between the first and second processing systems. The first and second processing systems may be simulated processing systems.

Abstract: Provided herein are methods, assays and compositions relating to the treatment of FSHD, particularly by modulating expression of DUX4.

Abstract: The present invention relates generally to the field of molecular biology and genetics. More particularly, it concerns methods and compositions for detecting, diagnosing, and/or treating facioscapulohumeral dystrophy (FSHD2).

Abstract: The invention is directed to 1-nitroacridine derivative(s)/tumor inhibitor(s) compositions as well as methods for using said compositions for inhibiting or preventing tumor growth, particularly, prostate cancer cell growth and metastases.

Abstract: Cellular DNA repair enzyme activity has been found to be an indicator of susceptibility or predisposition of an individual to DNA associated diseases. The activity of the enzyme adenosine diphosphate ribosyl transferase (ADPRT) has been found to be a good indicator as to the susceptibility of an individual to DNA associated diseases, such as cancer.

Abstract: A composition consisting essentially of human leukocyte interferon and an antiviral surfactant, such as the non-ionic surfactant, nonylphenoxypolyethoxy ethanol, and a physiologically acceptable carrier therefor, has been found to be useful for the treatment of malignant and pre-malignant skin lesions and skin lesions associated with herpes zoster and psoriasis by topically administering or applying the composition to the affected skin area.

Abstract: An electronics circuit for improving the fault isolation of failures between an electron tube radio frequency (RF) amplifier and its high voltage power supply is disclosed. High voltage power supplies control their output voltage by comparing a feedback voltage against a reference. This comparison is used to develop an error voltage which, in turn, drives a pulsewidth modulator that corrects the feedback voltage to the reference. The output of a digital-to-analog converter (DAC) is used as the reference voltage. The DAC is driven by a counter which would count to the correct reference voltage represented by a specific count. The final count is determined by a comparator which compares the counter output to the desired final count and stops the counter when it is reached.

Abstract: The high voltage field effect transistor has a drive circuit for pulse width modulation, which includes a small transformer coupled to the gate and source with a diode in series at the gate, so that a very short on-drive pulse charges the gate capacitance, and the charge is held by the diode. Another FET has its output connected between the gate and source of the high voltage FET, and its input coupled to another small transformer so that it is turned on for a short time by a very short off-drive pulse to discharge the gate capacitance and thus turn off the high voltage FET. A transformer drive circuit includes two one-shot devices connected to the pulse width modulator as leading and trailing edge detectors respectively, with their outputs connected via FET's to the on-drive and off-drive transformer primaries respectively, to provide pulses of 100-200 nanoseconds.

Abstract: High voltage FET's (field effect transistors) are used to modulate a traveling wave tube, which makes it possible to achieve fast rise, fall and delay chracteristics, and very long pulsewidths to CW because of their low drive requirements to maintain the on condition. The low and high voltage portions of the modulator are coupled via special transformers having only one or two turns for each winding on torroidal cores. Since such transformers are not adequate for long pulse widths, the gate to source capacitance of a high voltage FET is charged with a short pulse from one transformer and held there by a blocking diode until it is removed by the off drive. To obtain pulse widths all the way out to CW, a regeneration circuit is incorporated in the low voltage circuitry so that if the commanded on time goes beyond a maximum time, successive pulses are generated to maintain the voltage between gate and source of the on FET.