Patents by Inventor Daniel L. Hillman
Daniel L. Hillman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11362645Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each power island of the plurality of power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: GrantFiled: July 14, 2020Date of Patent: June 14, 2022Assignee: Mosaid Technologies IncorporatedInventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
-
Publication number: 20210036689Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: ApplicationFiled: July 14, 2020Publication date: February 4, 2021Inventors: Barry Alan HOBERMAN, Daniel L. HILLMAN, Jon Shiell
-
Patent number: 10749506Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within said each power island. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of said one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of said one power island of the plurality of power islands to the target power level.Type: GrantFiled: December 20, 2018Date of Patent: August 18, 2020Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
-
Patent number: 10424393Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.Type: GrantFiled: December 20, 2017Date of Patent: September 24, 2019Assignee: SPIN MEMORY, INC.Inventors: Mourad El Baraji, Neal Berger, Benjamin Stanley Louie, Lester M. Crudele, Daniel L. Hillman, Barry Hoberman
-
Patent number: 10366774Abstract: Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.Type: GrantFiled: September 27, 2016Date of Patent: July 30, 2019Assignee: Spin Memory, Inc.Inventors: Mourad El Baraji, Neal Berger, Benjamin Stanley Louie, Lester M. Crudele, Daniel L. Hillman, Barry Hoberman
-
Patent number: 10366775Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.Type: GrantFiled: December 20, 2017Date of Patent: July 30, 2019Assignee: SPIN MEMORY, INC.Inventors: Mourad El-Baraji, Neal Berger, Benjamin Stanley Louie, Lester M Crudele, Daniel L Hillman, Barry Hoberman
-
Publication number: 20190173453Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: ApplicationFiled: December 20, 2018Publication date: June 6, 2019Inventors: Barry Alan HOBERMAN, Daniel L. HILLMAN, Jon Shiell
-
Patent number: 10243542Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: GrantFiled: April 18, 2017Date of Patent: March 26, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
-
Patent number: 10200015Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands wherein a power consumption of each power island within the plurality of power islands is independently controlled within each of the power islands. A power manager determines a target power level for one power island of the plurality of power islands. The power manager then determines an action to change a consumption power level of the one power island of the plurality of power islands to the target power level. The power manager performs the action to change the consumption power level of the one power island of the plurality of power islands to the target power level.Type: GrantFiled: April 18, 2017Date of Patent: February 5, 2019Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry Alan Hoberman, Daniel L. Hillman, Jon Shiell
-
Publication number: 20180114589Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Mourad EL-BARAJI, Neal BERGER, Benjamin Stanley LOUIE, Lester M. CRUDELE, Daniel L. HILLMAN, Barry HOBERMAN
-
Publication number: 20180114590Abstract: Dynamic redundancy buffers for use with a device are disclosed. The dynamic redundancy buffers allow a memory array of the device to be operated with high write error rate (WER). A first level redundancy buffer (e1 buffer) is couple to the memory array. The e1 buffer may store data words that have failed verification or have not been verified. The e1 buffer may transfer data words to another dynamic redundancy buffer (e2 buffer). The e1 buffer may transfer data words that have failed to write to a memory array after a predetermined number of re-write attempts. The e1 buffer may also transfer data words upon power down.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Mourad EL-BARAJI, Neal BERGER, Benjamin Stanley LOUIE, Lester M CRUDELE, Daniel L HILLMAN, Barry HOBERMAN
-
Publication number: 20180090226Abstract: Dynamic redundancy registers for use with a device are disclosed. The dynamic redundancy registers allow a memory bank of the device to be operated with high write error rate (WER). A first level redundancy register (e1 register) is couple to the memory bank. The e1 register may store data words that have failed verification or have not been verified. The e1 register may transfer data words to another dynamic redundancy register (e2 register). The e1 register may transfer data words that have failed to write to a memory bank after a predetermined number of re-write attempts. The e1 register may also transfer data words upon power down.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Mourad EL BARAJI, Neal BERGER, Benjamin Stanley LOUIE, Lester M. CRUDELE, Daniel L. HILLMAN, Barry Hoberman
-
Publication number: 20170288649Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.Type: ApplicationFiled: April 18, 2017Publication date: October 5, 2017Applicant: Conversant Intellectual Property Management Inc.Inventors: Barry Alan HOBERMAN, Daniel L. HILLMAN, Jon Shiell
-
Patent number: 9722605Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: April 25, 2016Date of Patent: August 1, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
-
Patent number: 9660616Abstract: Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.Type: GrantFiled: September 25, 2015Date of Patent: May 23, 2017Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry Alan Hoberman, Daniel L Hillman, Jon Shiell
-
Publication number: 20160315615Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: April 25, 2016Publication date: October 27, 2016Applicant: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
-
Patent number: 9350349Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: GrantFiled: September 8, 2014Date of Patent: May 24, 2016Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole
-
Publication number: 20160087608Abstract: Systems and methods manage power in an integrated circuit using power islands. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level.Type: ApplicationFiled: September 25, 2015Publication date: March 24, 2016Applicant: Conversant Intellectual Property Management Inc.Inventors: Barry Alan HOBERMAN, Daniel L HILLMAN, Jon Shiell
-
Patent number: 9166412Abstract: A system for an integrated circuit comprising a plurality of power islands includes a first power manager and a second power manager. The first power manager manages a first power consumption for the integrated circuit based on needs and operation of the integrated circuit. The second power manager communicates with the first power manager and manages a second power consumption for one of the power islands.Type: GrantFiled: July 7, 2014Date of Patent: October 20, 2015Assignee: Conversant Intellectual Property Management Inc.Inventors: Barry Alan Hoberman, Daniel L Hillman, Jon Shiell
-
Publication number: 20140375354Abstract: An integrated circuit includes first circuitry and sleep transistor circuitry. The first circuitry receives input signals and processes the input signals. The first circuitry also retains data in a sleep state that has low leakage. The sleep transistor circuitry is coupled to the first circuitry and receives a sleep signal that has a negative voltage. The sleep circuitry reduces power consumption of the first circuitry in the sleep state to have low leakage based on the sleep signal while retaining the data in the first circuitry.Type: ApplicationFiled: September 8, 2014Publication date: December 25, 2014Inventors: Barry A. Hoberman, Daniel L. Hillman, William G. Walker, John M. Callahan, Michael A. Zampaglione, Andrew Cole