Abstract: A method for on-the fly updating of a processing circuit, the method includes monitoring, by multiple coroutines and during a monitoring period, a progress of multiple suspend-update-resume sequences executed by the processing circuit, wherein at least some of the multiple execute and suspend-update-resume sequences partially overlap and are not mutually synchronized, and wherein each suspend-update-resume sequence comprises on-the-fly updates; and determining, by a merged coroutine, timings of the multiple suspend-update-resume sequences, wherein the determining comprises performing multiple calculation iterations, wherein a calculation iteration of the multiple calculation iterations comprises calculating, in a an iterative manner, a timing of a next suspend-update-resume sequence to be executed out of the multiple suspend-update-resume sequences, and wherein the calculating is responsive to timing offsets between different suspend-update-resume sequences.

Abstract: A method for configuring a processing circuit, the method may include (i) receiving, by the processing circuit, a compressed configuration information data structure (CCDS) that comprises multiple segments, wherein the CCDS was generated by a size-preserving compression process that maintains a size of the segments; (ii) decompressing the CCDS, by the processing circuit, to provide decompressed configuration information, wherein the decompressing comprises: searching for headers, wherein a header comprises sequence parameters, wherein the sequence parameters comprise at least one out of a length, an address field, and a type; and (iii) configuring the processing circuit using the decompressed configuration information, wherein the configuring is executed based on the headers.

Abstract: A method for neural network convolution, the method may include receiving input data that is a 3D input data and comprises input data segments associated with different input data depth values; receiving a convolution kernel that is a 3D convolution kernel and comprises kernel segments associated with different kernel depth values; performing multiple 3D convolution iteration, wherein each of 3D convolution iteration comprises: determining whether the 3D convolution iteration is of a first type or of a second type; executing the 3D convolution iteration of the first type when determining that the 3D convolution iteration is of the first type; and executing the 3D convolution iteration of the second type when determining that the 3D convolution iteration is of the second type.

Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.

Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.

Abstract: A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

Abstract: A method of calculating warp results for at least one out of driver assistance and autonomous driving, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that includes: (a) Receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel. (b) Receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel (c) Calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights (d) And providing the warp result to a memory module.

Abstract: There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.

Abstract: A method of calculating warp results, the method may include executing, for each target pixel out of a group of target pixels, a warp calculation process that comprises: receiving, by a first group of processing units of an array of processing units, a first weight and a second weight associated with the target pixel; receiving, by a second group of processing units of the array, values of neighboring source pixels associated with the target pixel; calculating, by the second group, a warp result based on in response to values of the neighboring source pixels and the pair of weights; and providing the warp result to a memory module.

Abstract: Parallel processing of an image using an array of addressable registers. Image features are extracted from the image. The image features are storable as data. According to respective values of a sorting key derived from a parameter of the data, the image features are sorted into N buckets. Using an array of M addressable registers, where M is less than N, the data are summed within the buckets to perform a histogram of the image features, according to values of a histogram key derived from said a parameter of the data.

Abstract: Parallel processing of an image using an array of addressable registers. Image features are extracted from the image. The image features are storable as data. According to respective values of a sorting key derived from a parameter of the data, the image features are sorted into N buckets. Using an array of M addressable registers, where M is less than N, the data are summed within the buckets to perform a histogram of the image features, according to values of a histogram key derived from said a parameter of the data.