Patents by Inventor Danny Pak-Chum Shum

Danny Pak-Chum Shum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10741552
    Abstract: Methods for preventing step-height difference of flash and logic gates in FinFET devices and related devices are provided. Embodiments include forming fins in flash and logic regions; recessing an oxide exposing an upper portion of the fins; forming an oxide liner over the upper portion in the flash region; forming a polysilicon gate over and perpendicular to the fins in both regions; removing the gate from the logic region and patterning the gate in the flash region forming a separate gate over each fin; forming an ONO layer over the gates in the flash region; forming a second polysilicon gate over and perpendicular to the fins in both regions; planarizing the second polysilicon gate exposing a portion of the ONO layer over the gates in the flash region; forming and patterning a hardmask, exposing STI regions between the flash and logic regions; and forming an ILD over the STI regions.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: August 11, 2020
    Assignee: GLOBALFOUNDERS SINGAPORE PTE. LTD.
    Inventors: Ming Zhu, Pinghui Li, Su Yi Susan Yeow, Yiang Aun Nga, Danny Pak-Chum Shum, Eng Huat Toh
  • Patent number: 10693054
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 23, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Wanbing Yi, Curtis Chun-I Hsieh, Yi Jiang, Juan Boon Tan, Benfu Lin
  • Patent number: 10685970
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: June 16, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Shyue Seng Tan, Danny Pak-Chum Shum
  • Patent number: 10636867
    Abstract: A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 28, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xinshu Cai, Shyue Seng Tan, Juan Boon Tan, Danny Pak-Chum Shum
  • Patent number: 10608046
    Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: March 31, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Publication number: 20200083237
    Abstract: In a non-limiting embodiment, a memory array is provided having a transistor device. The transistor device includes transistor device first, second and third doped regions in a substrate. The transistor device further includes a first transistor device select gate over a region between the transistor device first doped region and the transistor device second doped region, and a second transistor device select gate over a region between the transistor device first doped region and the transistor device third doped region. The transistor device further includes a transistor device dielectric barrier extending between the first transistor device select gate and the second transistor device select gate. A width of the dielectric barrier compared to a width of the first transistor device select gate and/or the second transistor device select gate may have a ratio ranging from 0.33:1 to 5:1.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Xinshu Cai, Shyue Seng Tan, Danny Pak-Chum Shum
  • Publication number: 20200035906
    Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Danny Pak-Chum SHUM, Wanbing YI, Curtis Chun-I HSIEH, Yi JIANG, Juan Boon TAN, Benfu LIN
  • Publication number: 20200019500
    Abstract: The present disclosure relates to split gate flash MLC based neuromorphic processing and method of making the same. Embodiments include MLC split-gate flash memory formed over a substrate, the MLC split-gate flash memory embedded with artificial neuromorphic processing to dynamically program and erase each cell of the MLC split-gate flash memory; and sense visual imagery by the artificial neuromorphic processing.
    Type: Application
    Filed: July 12, 2018
    Publication date: January 16, 2020
    Inventors: Danny Pak-Chum SHUM, Shyue Seng TAN, Xinshu CAI, Fan ZHANG, Soh Yun SIAH, Tze Ho Simon CHAN
  • Publication number: 20200020761
    Abstract: A method of forming an integrated circuit with a metal-insulator-poly (MIP) capacitor formed in a high-k metal gate (HKMG) process and the resulting device are provided. Embodiments include a device including a metal gate; a high-k dielectric layer formed around side walls of the metal gate, and a dummy polysilicon gate adjacent to at least one portion of the high-k dielectric layer. The device also includes a capacitor including the HK layer as an insulator, wherein the insulator is between a dummy as one electrode and the metal gate as another electrode.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Xinshu CAI, Shyue Seng TAN, Juan Boon TAN, Danny Pak-Chum SHUM
  • Patent number: 10515679
    Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 24, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Jaiswal, Ajey P. Jacob, Bipul C. Paul, William Taylor, Danny Pak-Chum Shum
  • Patent number: 10510392
    Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Bipul C. Paul, Akhilesh Jaiswal, Ajey Poovannummoottil Jacob, William Taylor, Danny Pak-Chum Shum
  • Patent number: 10510946
    Abstract: Emerging memory chips and methods for forming an emerging memory chip are presented. For example, magnetic random access memory (MRAM) chip magnetic shielding and methods of forming a magnetic shield processed at the wafer-level are disclosed. The method includes providing a magnetic shield at the front side of the chip, back side of the chip, and also in the deep trenches surrounding or adjacent to magnetic tunnel junction (MTJ) array within the prime die region. Magnetic shield in the deep trenches connects front side and back side magnetic shield. This magnetic shielding method is applicable for both in-plane and perpendicular MRAM chips. The MTJ array is formed in the prime die region and in between adjacent inter layer dielectric (ILD) levels of the upper ILD layer in the back end of line (BEOL) of the MRAM chip.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Wanbing Yi, Danny Pak-Chum Shum, Shan Gao, Kangho Lee
  • Publication number: 20190378848
    Abstract: A method of forming a low-cost and compact hybrid SOI and bulk MTP cell and the resulting devices are provided. Embodiments include forming a bulk region in a SOI wafer; forming an NW in the bulk region and a PW in a remaining SOI region of the SOI wafer; forming first and second pairs of common FG stacks over both of the SOI and bulk regions; forming a first shared N+ RSD between each common FG stack of the first and second pairs in a top Si layer; forming a N+ RSD in the top Si layer of the SOI region on an opposite side of each common FG stack from the first shared N+ RSD; forming a second shared N+ RSD between each common FG stack in the bulk region; and forming a P+ RSD between the first and second pairs in the bulk region.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Eng Huat TOH, Shyue Seng TAN, Danny Pak-Chum SHUM
  • Patent number: 10461247
    Abstract: Device and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first, second and third regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the first and second regions. A MRAM cell which includes a MTJ element sandwiched between top and bottom electrodes is formed in the second region. The bottom electrode is in direct contact with the metal line in the first upper interconnect level of the second region. A dielectric layer which includes a second upper interconnect level with a dual damascene interconnect in the first region and a damascene interconnect in the second region is provided over the first upper dielectric layer. The dual damascene interconnect in the first region is coupled to the metal line in the first region and the damascene interconnect in the second region is coupled to the MTJ element.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: October 29, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Danny Pak-Chum Shum, Juan Boon Tan, Yi Jiang, Wanbing Yi, Francis Yong Wee Poh, Hai Cong
  • Publication number: 20190326352
    Abstract: Devices and methods of forming a device. A two-terminal device element includes a device stack coupled between first and second terminals. The first terminal contacts a metal line in an underlying interconnect level, and the second terminal is formed over the device layer. An encapsulation liner covers exposed side surfaces of the device stack of the two-terminal device element. A dual damascene interconnect is coupled to the two-terminal device element.
    Type: Application
    Filed: July 5, 2019
    Publication date: October 24, 2019
    Inventors: Wanbing YI, Curtis Chun-I HSIEH, Juan Boon TAN, Soh Yun SIAH, Hai CONG, Alex SEE, Young Seon YOU, Danny Pak-Chum SHUM, Hyunwoo YANG
  • Patent number: 10446607
    Abstract: Devices and methods of forming a device are disclosed. The method includes providing a substrate and a first upper dielectric layer over first and second regions of the substrate. The first upper dielectric layer includes a first upper interconnect level with a plurality of metal lines in the regions. A two-terminal device element which includes a device layer coupled in between first and second terminals is formed over the first upper dielectric layer in the second region. The first terminal contacts the metal line in the first upper interconnect level of the second region and the second terminal is formed on the device layer. An encapsulation liner covers at least exposed side surfaces of the device layer of the two-terminal device element. A dielectric layer which includes a second upper interconnect level with dual damascene interconnects is provided in the regions.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 15, 2019
    Assignee: GLOBALFOUNDARIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Curtis Chun-I Hsieh, Juan Boon Tan, Soh Yun Siah, Hai Cong, Alex See, Young Seon You, Danny Pak-Chum Shum, Hyunwoo Yang
  • Publication number: 20190305041
    Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.
    Type: Application
    Filed: June 17, 2019
    Publication date: October 3, 2019
    Inventors: Pinghui LI, Haiqing ZHOU, Liying ZHANG, Wanbing YI, Ming ZHU, Danny Pak-Chum SHUM, Darin CHAN
  • Patent number: 10431732
    Abstract: Shielded semiconductor devices and methods for fabricating shielded semiconductor devices are provided. An exemplary magnetically shielded semiconductor device includes a substrate having a top surface and a bottom surface. An electromagnetic-field-susceptible semiconductor component is located on and/or in the substrate. The magnetically shielded semiconductor device includes a top magnetic shield located over the top surface of the substrate. Further, the magnetically shielded semiconductor device includes a bottom magnetic shield located under the bottom surface of the substrate. Also, the magnetically shielded semiconductor device includes a sidewall magnetic shield located between the top magnetic shield and the bottom magnetic shield.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 1, 2019
    Assignees: GLOBALFOUNDRIES SINGAPORE PTE. LTD., AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH
    Inventors: Bhushan Bharat, Shan Gao, Danny Pak-Chum Shum, Wanbing Yi, Juan Boon Tan, Wei Yi Lim, Teck Guan Lim, Michael Han Kim Kwong, Eva Wai Leong Ching
  • Publication number: 20190287921
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Application
    Filed: June 5, 2019
    Publication date: September 19, 2019
    Inventors: Bharat BHUSHAN, Juan Boon TAN, Boo Yang JUNG, Wanbing YI, Danny Pak-Chum SHUM
  • Patent number: 10411027
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a fin extending from the substrate. The fin includes a first and second fin sidewall, and a memory cell layer is adjacent to the first and second fin sidewalls. A first control gate is adjacent to the memory cell layer where the memory cell layer is between the first fin sidewall and the first control gate. A second control gate is also adjacent to the memory cell layer, where the memory cell layer is between the second fin sidewall and the second control gate. The first and second control gates are electrically isolated from each other.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: September 10, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Ming Zhu, Pinghui Li, Eng Huat Toh, Yiang Aun Nga, Danny Pak-Chum Shum