Patents by Inventor Dariusz Czysz
Dariusz Czysz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20180143249Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: January 19, 2018Publication date: May 24, 2018Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
-
Patent number: 9874606Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: GrantFiled: June 21, 2016Date of Patent: January 23, 2018Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
-
Publication number: 20170052227Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: June 21, 2016Publication date: February 23, 2017Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee
-
Patent number: 9377508Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: GrantFiled: April 21, 2014Date of Patent: June 28, 2016Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
-
Patent number: 8832512Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.Type: GrantFiled: March 16, 2011Date of Patent: September 9, 2014Assignee: Mentor Graphics CorporationInventors: Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
-
Publication number: 20140229779Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
-
Patent number: 8726113Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: GrantFiled: April 23, 2012Date of Patent: May 13, 2014Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
-
Patent number: 8347159Abstract: The test data compression scheme is based on deterministic vector clustering. Test cubes that feature many similar specified bits are merged into a parent pattern in the presence of conflicts. The parent pattern along with a control pattern and incremental patterns representing conflicting bits are encoded efficiently. A tri-modal decompressor may be used to decompress the test data.Type: GrantFiled: March 5, 2010Date of Patent: January 1, 2013Assignee: Mentor Graphics CorporationInventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer
-
Patent number: 8301945Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: GrantFiled: September 2, 2011Date of Patent: October 30, 2012Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
-
Patent number: 8290738Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: GrantFiled: March 16, 2011Date of Patent: October 16, 2012Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
-
Publication number: 20120210181Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: ApplicationFiled: April 23, 2012Publication date: August 16, 2012Inventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
-
Patent number: 8166359Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.Type: GrantFiled: December 22, 2008Date of Patent: April 24, 2012Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Jerzy Tyszer
-
Publication number: 20110320999Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: ApplicationFiled: September 2, 2011Publication date: December 29, 2011Inventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
-
Patent number: 8046653Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: GrantFiled: August 11, 2010Date of Patent: October 25, 2011Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
-
Publication number: 20110231721Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for power aware test applications involving deterministic clustering of test cubes with conflicts. Embodiments of the disclosed technology can be used to generate low toggling parent patterns to reduce power consumption during testing an integrated circuit. The power consumption may be further reduced by generating low toggling control patterns.Type: ApplicationFiled: March 16, 2011Publication date: September 22, 2011Inventors: DARIUSZ CZYSZ, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Przemyslaw Szczerbicki, Jerzy Tyszer
-
Patent number: 8015461Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: GrantFiled: December 17, 2009Date of Patent: September 6, 2011Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
-
Publication number: 20110166818Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Inventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
-
Patent number: 7925465Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: GrantFiled: February 12, 2008Date of Patent: April 12, 2011Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
-
Publication number: 20100306609Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: ApplicationFiled: August 11, 2010Publication date: December 2, 2010Inventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer
-
Patent number: 7797603Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.Type: GrantFiled: July 19, 2007Date of Patent: September 14, 2010Inventors: Janusz Rajski, Grzegorz Mrugalski, Dariusz Czysz, Jerzy Tyszer