Abstract: A transistor device includes one or more conductive structures on which a cladding layer is formed, where the cladding layer has low miscibility with conductive material of the conductive structures at temperatures below a threshold. Such conductive structures may include gate (control) electrodes or drain and source (current-carrying) electrodes. Forming such a cladded conductive structure for a transistor device may include forming photoresist layers on a substrate, selectively patterning the photoresist layers to form openings therein, forming conductive material over the photoresist layers and on the substrate in openings in the photoresist layers, and forming a cladding layer over the conductive material, then preforming a lift-off process in which the photoresist layers are removed along with portions of the conductive material and cladding layer that are not disposed in the openings in the photoresist layers.

Abstract: A transistor formed in a semiconductor substrate is provided with a cooling trench. The cooling trench is elongated and extends laterally from a first end of an elongated gate electrode disposed above a channel region of the transistor to a second end of the gate electrode in a first direction that is parallel to a top surface of the semiconductor substrate. The cooling trench is coupled to the first current terminal and extends laterally from a first end to a second end of the first elongated cooling trench along the first direction and extends vertically from the first current terminal and through the top surface into the semiconductor substrate. The cooling trench is filled throughout with a thermally-conductive material configured to dissipate heat from the channel region into the semiconductor substrate.

Abstract: An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.

Abstract: A transistor includes first and second sets of gate fingers formed in an active area of a semiconductor substrate, an input bond pad formed in the semiconductor substrate and spaced apart from the active area, a first conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the first set of gate fingers, and a second conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the second set of gate fingers. A non-conductive gap is present between the distal ends of the first and second conductive structures. The transistor further includes an odd-mode oscillation stabilization circuit that includes a first resistor with a first terminal coupled to the distal end of the first conductive structure, and a second terminal coupled to the distal end of the second conductive structure.

Abstract: An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel, the length of the gate structure can be advantageously decreased.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed over the substrate. Forming the gate structure may include steps of forming a multi-layer dielectric stack over the substrate, performing an anisotropic dry etch of the multi-layer dielectric stack to form a gate channel opening, forming a conformal dielectric layer over the substrate, performing an anisotropic dry etch of the conformal dielectric layer to form dielectric sidewalls in the gate channel opening, etching portions of dielectric layers in a gate channel region, and forming gate metal in the gate channel region. Dielectric spacers may be similarly formed in a field plate channel opening prior to formation of a field plate of the transistor. By forming dielectric spacers in the gate channel opening, the length of the gate structure can be advantageously decreased.

Abstract: An integrated circuit includes an isolation test structure (ITS) formed in a non-active region. An electrical isolation between structures of the integrated circuit may be validated based on a measured resistance or conductivity across the ITS. In some embodiments the ITS includes interdigitated buffer layer structures. In some embodiments, the ITS is arranged in series with a test Through-substrate via (TSV). The test TSV is formed with a slower etch rate and smaller diameter than other standard TSVs of the integrated circuit and can be used to validate the formation of the standard TSVs based on measured resistance or conductivity thereof. By arranging the ITS and the test TSV in series, isolation of the integrated circuit and formation of TSVs in the integrated circuit can be validated using a single measurement.

Abstract: A transistor device includes a semiconductor substrate and a gate structure formed at the upper surface of the substrate. The gate structure includes a metal gate electrode and a gate insulating layer overlying the metal gate electrode, where edges of the gate insulating layer correspond to edges of the metal gate electrode. The transistor device also includes a first dielectric layer formed over the gate structure, and a first interconnect metal layer formed over the first dielectric layer. A portion of the first interconnect metal layer forms a field plate proximate to the gate structure, and a portion of the gate insulating layer and a portion of the first dielectric layer are present between the gate electrode and the field plate.

Abstract: A transistor device includes a semiconductor substrate and a gate structure at the upper surface of the substrate. The gate structure is non-planar and includes a metal gate electrode with first and second sidewalls. A first dielectric layer is present over the gate structure. The first dielectric layer includes a first portion that overlies the first sidewall and a second portion that overlies the second sidewall. A portion of a conductive layer over the first dielectric layer forms a field plate with a first portion proximate to the second sidewall of the gate structure. A dielectric sidewall spacer on the first portion of the field plate is formed from a portion of a second dielectric layer, and the dielectric sidewall spacer does not contact the first dielectric layer.

Abstract: An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Abstract: A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist (1703, 1704) on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (1705), where the patterned photoresist mask is removed (1706) from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices (1708) which each include a unique die marking.

Abstract: Power amplifier (PA) devices and methods for fabricating PA devices containing inverted power transistor dies are disclosed. In embodiments, the PA device includes a first set of input and output leads, an inverted first power transistor (e.g., peaking) die electrically coupled between the first set of input and output leads, and a base flange. The inverted first power die includes, in turn, a die body having a die frontside and a die backside opposite the die frontside. A power transistor having a first contact region is formed in the die frontside. A frontside layer system is formed over the die frontside and the power transistor, while an electrically-conductive bond layer attaches the inverted first power transistor die to the base flange. The first contact region of the power transistor is electrically coupled to the base flange through the electrically-conductive bond layer and through the frontside layer system.

Abstract: A power transistor die includes a semiconductor die with input and output die sides, and a transistor integrally formed in the semiconductor die between the input die side and the output die side, where the transistor has an input and an output (e.g., a gate and a drain, respectively). The power transistor die also includes an input bondpad and a first output bondpad integrally formed in the semiconductor die between the input die side and the transistor. The input bondpad is electrically connected to the input of the transistor. A conductive structure directly electrically connects the output of the transistor to the first output bondpad. A second output bondpad, which also may be directly electrically connected to the transistor output, may be integrally formed in the semiconductor die between the transistor and the output die side.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with a contact region formed within the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer.

Abstract: Power amplifier (PA) devices and methods for fabricating PA devices containing inverted power transistor dies are disclosed. In embodiments, the PA device includes a first set of input and output leads, an inverted first power transistor (e.g., peaking) die electrically coupled between the first set of input and output leads, and a base flange. The inverted first power die includes, in turn, a die body having a die frontside and a die backside opposite the die frontside. A power transistor having a first contact region is formed in the die frontside. A frontside layer system is formed over the die frontside and the power transistor, while an electrically-conductive bond layer attaches the inverted first power transistor die to the base flange. The first contact region of the power transistor is electrically coupled to the base flange through the electrically-conductive bond layer and through the frontside layer system.

Abstract: A transistor includes an active region bounded by an outer periphery and formed in a substrate. The active region includes sets of input fingers, output fingers, and common fingers disposed within the substrate and oriented substantially parallel to one another. The transistor further includes an input port, an output port, a first via connection disposed at the outer periphery of the active region proximate the input port and a second via connection disposed at the outer periphery of the active region proximate the output port. The second via connection has a noncircular cross-section with a second major axis and a second minor axis, the second major axis having a second major axis length, the second minor axis having a second minor axis length that is less than the second major axis length. The second major axis is oriented parallel to a longitudinal dimension of the input, output, and common fingers.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.