Patents by Inventor David A. Asson
David A. Asson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180323896Abstract: A satellite communications system can use a spread-spectrum waveform and format, a synchronization scheme, and/or a power management algorithm. This approach can provide benefits such as allowing every terminal to communicate with every other terminal, link margin permitting. This gives the network a mesh topology although it can be configured in a star topology for highly asymmetric applications. A further understanding of the nature and the advantages of particular embodiments disclosed herein may be realized by reference of the remaining portions of the specification and the attached drawings.Type: ApplicationFiled: May 4, 2018Publication date: November 8, 2018Inventors: Nathan Hays, David Asson
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Patent number: 9991984Abstract: A satellite communications system can use a spread-spectrum waveform and format, a synchronization scheme, and/or a power management algorithm. This approach can provide benefits such as allowing every terminal to communicate with every other terminal, link margin permitting. This gives the network a mesh topology although it can be configured in a star topology for highly asymmetric applications. A further understanding of the nature and the advantages of particular embodiments disclosed herein may be realized by reference of the remaining portions of the specification and the attached drawings.Type: GrantFiled: August 26, 2016Date of Patent: June 5, 2018Assignee: Terrace Communications CorporationInventors: Nathan Hays, David Asson
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Publication number: 20170111135Abstract: A satellite communications system can use a spread-spectrum waveform and format, a synchronization scheme, and/or a power management algorithm. This approach can provide benefits such as allowing every terminal to communicate with every other terminal, link margin permitting. This gives the network a mesh topology although it can be configured in a star topology for highly asymmetric applications. A further understanding of the nature and the advantages of particular embodiments disclosed herein may be realized by reference of the remaining portions of the specification and the attached drawings.Type: ApplicationFiled: August 26, 2016Publication date: April 20, 2017Inventors: Nathan Hays, David Asson Asson
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Patent number: 8099708Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.Type: GrantFiled: April 30, 2009Date of Patent: January 17, 2012Assignee: LSI CorporationInventors: Grant Lindberg, Gregor J. Martin, David Asson, Ying Chun He
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Publication number: 20090210846Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.Type: ApplicationFiled: April 30, 2009Publication date: August 20, 2009Inventors: Grant Lindberg, Gregor J. Martin, David Asson, Ying Chun He
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Patent number: 7543261Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.Type: GrantFiled: April 27, 2005Date of Patent: June 2, 2009Assignee: LSI CorporationInventors: Grant Lindberg, Gregor J. Martin, David Asson, Ying Chun He
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Patent number: 7474121Abstract: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM.Type: GrantFiled: December 13, 2005Date of Patent: January 6, 2009Assignee: Altera CorporationInventors: David A. Asson, James Macarthur
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Publication number: 20060248491Abstract: A method of operation for an input/output assignment tool is disclosed. The method generally includes the steps of (A) generating a graphic presentation to a user displaying (i) a circuit icon having a plurality of pin icons and (ii) a plurality of signal icons, (B) moving a first of the signal icons within the graphic presentation to a first of the pin icons in response to a move command from the user and (C) indicating an acceptance of an association between the first signal icon and the first pin icon in response to the association passing a rule.Type: ApplicationFiled: April 27, 2005Publication date: November 2, 2006Inventors: Grant Lindberg, Gregor Martin, David Asson, Ying He
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Patent number: 7000165Abstract: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM.Type: GrantFiled: October 9, 2002Date of Patent: February 14, 2006Assignee: Altera CorporationInventors: David A. Asson, James B. MacArthur
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Patent number: 6492833Abstract: A mask programmable integrated circuit includes a read only memory (ROM), a random access memory (RAM), and a controller. The controller couples to the ROM and RAM. The controller senses a reset condition and, in response, directs a clear of the RAM or a preload of contents of the ROM to the RAM. The preload can be performed after a successful self-test of the RAM is achieved. The RAM has a variable word length and depth size and can be configured to operate in one of many modes. The integrated circuit further includes a first and a second multiplexer (MUX). The first MUX is interposed between the RAM and the ROM, and selectively couples either the ROM data or the built-in self-test (BIST) data to the first MUX output. The second MUX is interposed between the first MUX and the RAM, and selectively couples either the output of the first MUX or a (synchronous or asynchronous) data input to the RAM.Type: GrantFiled: April 28, 1999Date of Patent: December 10, 2002Assignee: Altera CorporationInventors: David A. Asson, James B. MacArthur
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Patent number: 5179375Abstract: A system for inputting signals to a terminal includes a first interface having an input port, the first interface including a decoder for decoding the signals received at said port for application to the terminal. Two external sources of signals are OR'ed to the same port. One or both the sources may include an external input device and an interface for translating signals from a first code output from the input device to a second code which the first interface is adapted to accept. In order to OR the outputs of the sources, the sources may have open collector output transistors connected to a common collector resistor in the first interface.Type: GrantFiled: August 7, 1990Date of Patent: January 12, 1993Assignee: Soricon CorporationInventors: Donald E. Dick, Randall M. Pierson, David A. Asson