Patents by Inventor David A. Grosch
David A. Grosch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9535113Abstract: A method, apparatus and computer program product for testing semiconductor products that combines multiple techniques. Depending on the requirements, different ones of the techniques are emphasized over the other techniques. The testing applies a technique to achieve a higher single defect acceleration parameter at the expense of a second parameter, thus enabling acceleration of defects that require higher voltage or higher temperature than a traditional “Burn In” can achieve, which defects would otherwise go unaccelerated. The method manages the adaptation of the different techniques, e.g., how it decides to favor one technique over the other, and how it carries out the favoring of one or more particular techniques in a given test situation. Thus, acceleration to defectivity (defect type and quantity) may be tailored in real time by uniquely leveraging the duration spent in a given section of a process flow based on the prevalence of unique defect types.Type: GrantFiled: January 21, 2016Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: David A. Grosch, Gregory V. Miller, Brian C. Noble, Ann L. Swift, Joel Thomas, Jody J. Van Horn
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Patent number: 8854073Abstract: Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.Type: GrantFiled: September 20, 2011Date of Patent: October 7, 2014Assignee: International Business Machines CorporationInventors: David A. Grosch, Marc D. Knox, Erik A. Nelson, Brian C. Noble
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Publication number: 20130069678Abstract: Method and apparatus for margin testing integrated circuits. The method includes selecting a clock frequency, an operating temperature range and a power supply voltage level for margin testing an integrated circuit wherein one or more of the clock frequency, the operating temperature range and the power supply voltage level is outside of the normal operating conditions of the integrated circuit; applying an asynchronously time varying power supply voltage set to the selected power supply voltage level to the integrated circuit; running the integrated circuit chip at the selected clock frequency and maintaining the integrated circuit within the selected temperature range; applying a continuous test pattern to the integrated circuit; and monitoring the integrated circuit for fails.Type: ApplicationFiled: September 20, 2011Publication date: March 21, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Grosch, Marc D. Knox, Erik A. Nelson, Brian C. Noble
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Patent number: 7759960Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: GrantFiled: April 16, 2008Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Anne E. Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Patent number: 7564256Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: GrantFiled: May 13, 2008Date of Patent: July 21, 2009Assignee: International Business Machines CompanyInventors: Anne Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Patent number: 7486098Abstract: A method for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The method improves the resolution of IDDQ testing and diagnosis by modifying well bias during testing. The method applies to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the method relies on using the well bias to change transistor threshold voltages.Type: GrantFiled: October 22, 2007Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Anne Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Publication number: 20080211531Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: ApplicationFiled: May 13, 2008Publication date: September 4, 2008Inventors: Anne E. Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Publication number: 20080211530Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: ApplicationFiled: April 16, 2008Publication date: September 4, 2008Inventors: Anne E. Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Patent number: 7400162Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: GrantFiled: February 20, 2003Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Anne Gattiker, David A. Grosch, Marc D. Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul S. Zuchowski
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Publication number: 20080036486Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: ApplicationFiled: October 22, 2007Publication date: February 14, 2008Inventors: Anne Gattiker, David Grosch, Marc Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul Zuchowski
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Publication number: 20060071653Abstract: Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.Type: ApplicationFiled: February 20, 2003Publication date: April 6, 2006Inventors: Anne Gattiker, David Grosch, Marc Knox, Franco Motika, Phil Nigh, Jody Van Horn, Paul Zuchowski