Patents by Inventor David A. Horine

David A. Horine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6861034
    Abstract: Provided is a priming mechanism for priming a biofluid drop ejection device having a drop ejection opening leading to an ejection reservoir. The priming mechanism includes a vacuum unit which generates a vacuum force, connected to a vacuum nozzle. The vacuum nozzle is located over the drop ejection opening. A disposable sleeve or tubing is attached to the vacuum nozzle and is placed in operational contact with the drop ejection opening. A fluid height detection sensor is positioned to sense a fluid height within at least one of the disposable tubing and the vacuum nozzle. Upon sensing a predetermined fluid height, by the fluid height detection sensor, the priming operation is completed, and the primer mechanism is removed from the operational contact with the drop ejection opening.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: March 1, 2005
    Assignee: Xerox Corporation
    Inventors: Scott A. Elrod, Joy Roy, Babur B. Hadimioglu, Richard H. Bruce, Jaan Noolandi, David A. Horine
  • Patent number: 6740530
    Abstract: Methods for testing proper operation of drop ejection units in a multi-ejector system are provided to determine whether the drop ejectors have been properly filled and/or the ejectors are emitting fully formed droplets. The methods include testing the ejectors prior to drop ejection. In this method, a priming system is used wherein fluid received by the priming system is ejected onto a test substrate to allow a scanner to determine the existence of the fluids at selected locations. The selected locations are correlated to the drop ejection units to determine which ejection units do not have biofluid or sufficient biofluid. A further method allows for ejection prior to printing, on a test substrate wherein testing for both the fullness of the ejector units as well as proper emission of the ejectors of droplets may be tested. The ejectors after being primed, eject the biofluids which are then scanned and correlated to each individual ejector.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: May 25, 2004
    Assignee: Xerox Corporation
    Inventors: Richard H. Bruce, Scott A. Elrod, Jaan Noolandi, David A. Horine, Babur B. Hadimioglu
  • Patent number: 6713022
    Abstract: A biofluid drop ejection unit for ejecting biofluid drops. A biofluid drop ejection mechanism of such a unit includes a transducer, which generates energy used to emit the biofluid drop. Further provided is a reagent cartridge or biofluid containment area which holds the biofluid. The reagent cartridge or biofluid containment area is configured to hold low volumes of biofluid and to avoid contamination of the biofluid. The reagent cartridge or biofluid containment area is in operational connection with the drop ejection mechanism such that upon operation of the drop ejection mechanism, biofluid drops are emitted. The biofluid drop ejection mechanism is a high efficiency device, and may be configured as two separate pieces or as a single disposable unit.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: March 30, 2004
    Assignee: Xerox Corporation
    Inventors: Jaan Noolandi, David A. Horine, Babur B. Hadimioglu, Richard H. Bruce, Joy Roy, Scott A. Elrod
  • Patent number: 6623700
    Abstract: A level control mechanism is provided for a biofluid drop ejection device which ejects biofluid drops in small volumes. The biofluid drop device includes a drop ejection mechanism having a transducer which generates energy used to emit the biofluid drops. A reagent cartridge or biofluid holding area holds a biofluid, isolated from the drop ejection mechanism to avoid contamination between the biofluid drop ejection mechanism and the reagent cartridge. The reagent cartridge is connected to the drop ejection mechanism such that upon operation of the mechanism, the biofluid is emitted in controlled biofluid drops. A level sensor is positioned to sense a height of the biofluid within the cartridge. Upon sensing the height of the biofluid below a certain level, an adjustment is made to the height by providing at least one of additional biofluid to the cartridge, and raising the level of the entire reagent cartridge.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: September 23, 2003
    Assignee: Xerox Corporation
    Inventors: David A. Horine, Babur B. Hadimioglu, Richard H. Bruce, Jaan Noolandi, Scott A. Elrod
  • Patent number: 6514704
    Abstract: A method and mechanism for ensuring quality control in printed biological assays is provided. A multi-ejector system having a plurality of individual drop ejectors is loaded with a variety of biofluids. Biofluids include at least a carrier fluid, a biological material to be used in the testing, and markers, such as fluorescent dyes. Data regarding the biofluid loaded in each of the drop ejectors is stored along with an expected signature output of the biofluid. Particularly, the signature output represents signals from individual ones of the fluorescent markers included within the biofluid. Once a biological assay consisting of the biofluid drops has been printed, a scanner capable of detecting the markers scans the biological assay and obtains signature output signals for each of the drops of the biological assay.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: February 4, 2003
    Assignee: Xerox Corporation
    Inventors: Richard H. Bruce, Scott A. Elrod, Babur B. Hadimioglu, David A. Horine, Jaan Noolandi, Joy Roy, Robert A. Sprague
  • Patent number: 6503454
    Abstract: A multiple-ejector system for printing arrays of biofluids include a tooling plate having a plurality of sets of tooling pins extending outward from the surface of the tooling plate. A printed circuit board is provided having pairs of power connection pins and ground return pins extending from a surface of the circuit board. A plurality of biofluid drop ejection units are provided and include alignment grooves and at least a transducer. Each of the plurality of biofluid drop ejection units are connected to a corresponding one of a set of tooling pins by connection of the tooling pins and alignment grooves. The power connection pins of the pairs are in operational connection with respective transducers and the ground return connection pins of the pairs are in operational connection with a body portion of the drop ejection units. The different drop ejection units will contain different biofluids which are to be emitted onto a substrate.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: January 7, 2003
    Assignee: Xerox Corporation
    Inventors: Babur B. Hadimioglu, Scott A. Elrod, Richard H. Bruce, Jaan Noolandi, David A. Horine
  • Publication number: 20020102555
    Abstract: A method and mechanism for ensuring quality control in printed biological assays is provided. A multi-ejector system having a plurality of individual drop ejectors is loaded with a variety of biofluids. Biofluids include at least a carrier fluid, a biological material to be used in the testing, and markers, such as fluorescent dyes. Data regarding the biofluid loaded in each of the drop ejectors is stored along with an expected signature output of the biofluid. Particularly, the signature output represents signals from individual ones of the fluorescent markers included within the biofluid. Once a biological assay consisting of the biofluid drops has been printed, a scanner capable of detecting the markers scans the biological assay and obtains signature output signals for each of the drops of the biological assay.
    Type: Application
    Filed: February 1, 2001
    Publication date: August 1, 2002
    Applicant: XEROX CORPORATION
    Inventors: Richard H. Bruce, Scott A. Elrod, Babur B. Hadimioglu, David A. Horine, Jaan Noolandi, Joy Roy, Robert A. Sprague
  • Patent number: 6350405
    Abstract: A method for manufacturing metal structures in which minute drops of a liquid metal are emitted from an acoustic device through an inert gas. The presence of the inert gas at the surface of the liquid metal prevent the formation of an oxide skin which would absorb acoustic energy and hinder droplet formation and emission. The droplets are then emitted towards a substrate, which may form as a carrier, where they may be used to form solder bumps, circuit traces, or accreted to form a three dimensional device.
    Type: Grant
    Filed: April 11, 2001
    Date of Patent: February 26, 2002
    Assignee: Xerox Corporation
    Inventor: David A. Horine
  • Publication number: 20010018851
    Abstract: A method for manufacturing metal structures in which minute drops of a liquid metal are emitted from an acoustic device through an inert gas. The presence of the inert gas at the surface of the liquid metal prevent the formation of an oxide skin which would absorb acoustic energy and hinder droplet formation and emission. The droplets are then emitted towards a substrate, which may form as a carrier, where they may be used to form solder bumps, circuit traces, or accreted to form a three dimensional device.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 6, 2001
    Applicant: Xerox Corporation
    Inventor: David A. Horine
  • Patent number: 6248151
    Abstract: A method for manufacturing metal structures in which minute drops of a liquid metal are emitted from an acoustic device through an inert gas. The presence of the inert gas at the surface of the liquid metal prevent the formation of an oxide skin which would absorb acoustic energy and hinder droplet formation and emission. The droplets are then emitted towards a substrate, which may form as a carrier, where they may be used to form solder bumps, circuit traces, or accepted to form a three dimensional device.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: June 19, 2001
    Assignee: Xerox Corporation
    Inventor: David A. Horine
  • Patent number: 6168971
    Abstract: A method of assembling thin film jumper connectors to a substrate as part of a process of manufacturing a multi-chip-module or other device having multiple components bonded to chip carrier or other substrate. An alignment plate is positioned on the chuck of a standard flip-chip bonding machine. The thin film jumper connectors are placed on the alignment plate in a face-up position after alignment to alignment marks on the plate using the machine's moveable platform and split-field viewer. The jumper connectors are held to the alignment plate by a force supplied by the vacuum system of the flip-chip bonder, with the force being transmitted to the jumpers through vacuum holes in the alignment plate. The plate's alignment marks are positioned so that when they are aligned with corresponding marks on the connectors, the bonding pads on the connectors are correctly aligned to the pads on the substrate.
    Type: Grant
    Filed: May 5, 1998
    Date of Patent: January 2, 2001
    Assignee: Fujitsu Limited
    Inventors: David G. Love, Patricia R. Boucher, David A. Horine
  • Patent number: 6034332
    Abstract: A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: March 7, 2000
    Assignee: Fujitsu Limited
    Inventors: Larry Louis Moresco, Richard L. Wheeler, Solomon I. Beilin, David A. Horine
  • Patent number: 6019814
    Abstract: A method for manufacturing precise complex three dimensional structures in which minute drops of both a product layer and a sacrificial layer are emitted from an acoustic device. The process is a two step process wherein first the three dimensional structure is built in layers which are composed of either a sacrificial layer or a product layer or some configuration of both. Once the structure has been completely built up, then the sacrificial layer is removed leaving only the complex three dimensional structure.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: February 1, 2000
    Assignee: Xerox Corporation
    Inventor: David A. Horine
  • Patent number: 6007183
    Abstract: A method for manufacturing metal structures in which minute drops of a liquid metal are emitted from an acoustic device through an inert gas. The presence of the inert gas at the surface of the liquid metal prevent the formation of an oxide skin which would absorb acoustic energy and hinder droplet formation and emission. The droplets are then emitted towards a substrate, which may form as a carrier, where they may be used to form solder bumps, circuit traces, or accreted to form a three dimensional device.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: December 28, 1999
    Assignee: Xerox Corporation
    Inventor: David A. Horine
  • Patent number: 5930890
    Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
    Type: Grant
    Filed: April 21, 1997
    Date of Patent: August 3, 1999
    Assignee: Fujitsu Limited
    Inventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang
  • Patent number: 5765279
    Abstract: A power distribution structure for a multichip module and a method for fabricating the same are shown. According to the method of the present invention, a base plate is provided, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is then formed over the exposed surfaces of the mesas and the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The resulting structure is then planarized, as by polishing, such that the upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material.
    Type: Grant
    Filed: May 22, 1995
    Date of Patent: June 16, 1998
    Assignee: Fujitsu Limited
    Inventors: Larry Louis Moresco, Richard L. Wheeler, Solomon I. Beilin, David A. Horine
  • Patent number: 5722162
    Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.
    Type: Grant
    Filed: October 12, 1995
    Date of Patent: March 3, 1998
    Assignee: Fujitsu Limited
    Inventors: William T. Chou, Solomon I. Beilin, David A. Horine, David Kudzuma, Michael G. Lee, Larry Louis Moresco, Wen-chou Vincent Wang
  • Patent number: 5655290
    Abstract: A three dimensional module for housing a plurality of integrated circuit chips is shown. The IC chips are mounted in rows on a plurality of substrates. Parallel to each row are communications bars which provide signal paths allowing chips on one substrate to communicate with those on another substrate. The communications bars also serve as spacers between substrates, thereby forming cooling channels. The IC chips are disposed in the cooling channels so that they come into direct contact with the cooling fluid. Signal lines to and from the IC chips are kept as separated as possible from the power lines so as to minimize noise. To this end, relatively thick power supply straps are mounted to each substrate below each row of IC chips. The power supply straps are, in turn, connected to power feed straps such that a very low impedance power supply path to the IC chips is maintained.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventors: Larry L. Moresco, David A. Horine, Wen-Chou Vincent Wang
  • Patent number: 5603892
    Abstract: A system for maintaining electronic components, such as integrated circuit chips, in a contaminant-free controlled atmosphere is disclosed. The components, which may be mounted on a multichip module, are housed in a sealed enclosure and a positive pressure of contaminant-free gas, such as pure nitrogen, is maintained within the enclosure. A source of pressurized gas, controllably connected to the enclosure is provided and, preferably, an exhaust valve is used to equalize the pressure in the enclosure when it is necessary to access the interior for purposes of maintenance or repair. Preferably, there is a control system which monitors and maintains the proper level of pressure within the enclosure and which may be used to periodically flush the enclosure. Also preferably, one or more canisters of getter material are attached to the enclosure for removing contaminants.
    Type: Grant
    Filed: June 9, 1994
    Date of Patent: February 18, 1997
    Assignee: Fujitsu Limited
    Inventors: Carlo Grilletto, David A. Horine
  • Patent number: 5536362
    Abstract: Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures.
    Type: Grant
    Filed: February 16, 1994
    Date of Patent: July 16, 1996
    Assignee: Fujitsu Limited
    Inventors: David G. Love, Larry L. Moresco, William Tai-Hua Chou, David A. Horine, Connie M. Wong, Solomon I. Beilin