Abstract: In one embodiment a method for handling shadow or overlay memories is described wherein a linker contains a description of the memory of a target embedded system so that each memory space is described for each state of the control devices. The linker in one embodiment contains the shadow memory configuration information so that post linker tools such as loaders and debuggers can utilize this information. The information for each configuration includes how to get the device into the state that makes each configuration visible in address space, how to get the device back into the state it was in before the state was changed and how to find out the state the device is in.

Abstract: The present invention provides a method for far branch and call instructions. The present invention includes the link-time modification of object code generated by the compiler or assembler and the addition of custom generated object code to the link for the purpose of implementing far branches and calls without changing the compiler generated instructions or expanding compiler generated object code.

Abstract: The present invention provides a visual linker. The visual linker includes a link server that implements linking instructions for sections to a memory. The visual linker also includes a graphical user interface that receives said instructions and displays said sections within said memory. The visual linker also includes an application programming interface that receives said instructions and reports the results of said linking instruction and said sections within said memory. The visual linker also includes an incomplete link comprising sections not allocated to said memory. The visual linker also includes a link recipe comprising said instructions implemented by said link server.

Abstract: In one embodiment a method for handling shadow or overlay memories is described wherein a linker contains a description of the memory of a target embedded system so that each memory space is described for each state of the control devices. The linker in one embodiment contains the shadow memory configuration information so that post linker tools such as loaders and debuggers can utilize this information. The information for each configuration includes how to get the device into the state that makes each configuration visible in address space, how to get the device back into the state it was in before the state was changed and how to find out the state the device is in.

Abstract: A system for allocating code sections to a plurality of processors is provided. The system includes a linker for allocating and linking the code sections. The system also includes at least one private memory on each of the plurality of processors. The system also includes at least one shared memory accessible by the plurality of processors. The system also includes at least one incomplete link corresponding to the code sections not allocated to the at least one shared memory and the at least one private memory.