Abstract: Systems and methods for power distribution by an ethernet controller are disclosed. A first input port receives a first power carried by a first ethernet cable and sourced by a first source PoE device. A second input port receives a second power carried by a second ethernet cable and sourced by a second source PoE device. The first input port is at a first voltage lower than a minimum voltage of a specified input voltage range and the second input port is at a second voltage lower than the minimum voltage of the specified input voltage range. A controller, coupled to the first and second input ports, substantially equalizes current flowing across a first output port and a second output port, coupled to the downstream PoE devices, such that a load, caused by the downstream PoE devices, between the first output port and the second output port is shared.

Abstract: A thermal management system is provided. The system includes a temperature sensor, a fan, an electronic circuit breaker (ECB) coupled to the fan to provide electric power to the fan. The system includes a controller coupled to the temperature sensor and the ECB, to direct the ECB to turn off the electric power to the fan responsive to detecting a temperature, from the temperature sensor less than a temperature threshold based on a temperature rating of the fan.

Abstract: Systems and methods for power distribution by an ethernet controller are disclosed. A first input port receives a first power carried by a first ethernet cable and sourced by a first source PoE device. A second input port receives a second power carried by a second ethernet cable and sourced by a second source PoE device. The first input port is at a first voltage lower than a minimum voltage of a specified input voltage range and the second input port is at a second voltage lower than the minimum voltage of the specified input voltage range. A controller, coupled to the first and second input ports, substantially equalizes current flowing across a first output port and a second output port, coupled to the downstream PoE devices, such that a load, caused by the downstream PoE devices, between the first output port and the second output port is shared.

Abstract: Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

Abstract: A thermal management system is provided. The system includes a temperature sensor, a fan, an electronic circuit breaker (ECB) coupled to the fan to provide electric power to the fan. The system includes a controller coupled to the temperature sensor and the ECB, to direct the ECB to turn off the electric power to the fan responsive to detecting a temperature, from the temperature sensor less than a temperature threshold based on a temperature rating of the fan.

Abstract: Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

Abstract: Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

Abstract: Methods and systems for handling a single event upset. The methods include, and/or the systems include functionality for, receiving, from a monitored device, data at a first input of an initial state change device; detecting, based on receiving the data, a state change; asserting, based on detecting the state change, an initial state change device enable signal; transferring the first data from the first input to a first output of the initial state change device (which may be operatively connected to a second input of a state hold device); triggering, based on detecting the state change, a delay counter; making a determination that the delay period counted by the delay counter expired without receipt of an error detection signal; and based on the determination, asserting a state hold device enable signal to allow the data to pass from the second input to a second output of the state hold device.

Abstract: A bidirectional clock synchronization circuit is provided. The circuit includes a bidirectional port having an input/output terminal and a transceiver, having a first interface with a unidirectional input and a unidirectional output, and a second interface with a bidirectional input/output coupled to the input/output terminal of the bidirectional port. The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop.