Patents by Inventor David Arditti Ilitzky
David Arditti Ilitzky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240311331Abstract: A best efforts (BE) hardware remote direct memory access (RDMA) transport being performed by a smart network interface controller (NIC). Elements from RoCEv2 and iWARP are utilized in combination with extensions to improve flexibility and packet error recovery. Flexibility is provided by allowing RDMA roles to be individually specified. Flexibility is also provided by additional packet numbering options to allow interleaving of request and response messages at a packet boundary. Error recovery is improved by utilized new acknowledgement responses, SNAK provided for each new hole detected and RACK for each received packet after a SNAK. SNAK allows the indication of resource exhaustion at the receiver, causing entry into a recovery mode where only packets in a hole are transmitted until resources are recovered.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: David Arditti Ilitzky, Linghe Wang, Brian Hausauer
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Publication number: 20240311322Abstract: A best efforts (BE) hardware remote direct memory access (RDMA) transport being performed by a smart network interface controller (NIC). Elements from RoCEv2 and iWARP are utilized in combination with extensions to improve flexibility and packet error recovery. Flexibility is provided by allowing RDMA roles to be individually specified. Flexibility is also provided by additional packet numbering options to allow interleaving of request and response messages at a packet boundary. Error recovery is improved by utilized new acknowledgement responses, SNAK provided for each new hole detected and RACK for each received packet after a SNAK. SNAK allows the indication of resource exhaustion at the receiver, causing entry into a recovery mode where only packets in a hole are transmitted until resources are recovered.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: Linghe Wang, David Arditti Ilitzky, Brian Hausauer
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Publication number: 20240311333Abstract: A best efforts (BE) hardware remote direct memory access (RDMA) transport being performed by a smart network interface controller (NIC). Elements from RoCEv2 and iWARP are utilized in combination with extensions to improve flexibility and packet error recovery. Flexibility is provided by allowing RDMA roles to be individually specified. Flexibility is also provided by additional packet numbering options to allow interleaving of request and response messages at a packet boundary. Error recovery is improved by utilized new acknowledgement responses, SNAK provided for each new hole detected and RACK for each received packet after a SNAK. SNAK allows the indication of resource exhaustion at the receiver, causing entry into a recovery mode where only packets in a hole are transmitted until resources are recovered.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: Linghe Wang, David Arditti Ilitzky, Brian Hausauer
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Publication number: 20240311332Abstract: A best efforts (BE) hardware remote direct memory access (RDMA) transport being performed by a smart network interface controller (NIC). Elements from RoCEv2 and iWARP are utilized in combination with extensions to improve flexibility and packet error recovery. Flexibility is provided by allowing RDMA roles to be individually specified. Flexibility is also provided by additional packet numbering options to allow interleaving of request and response messages at a packet boundary. Error recovery is improved by utilized new acknowledgement responses, SNAK provided for each new hole detected and RACK for each received packet after a SNAK. SNAK allows the indication of resource exhaustion at the receiver, causing entry into a recovery mode where only packets in a hole are transmitted until resources are recovered.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: David Arditti Ilitzky, Linghe Wang, Brian Hausauer
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Publication number: 20240314203Abstract: A best efforts (BE) hardware remote direct memory access (RDMA) transport being performed by a smart network interface controller (NIC). Elements from RoCEv2 and iWARP are utilized in combination with extensions to improve flexibility and packet error recovery. Flexibility is provided by allowing RDMA roles to be individually specified. Flexibility is also provided by additional packet numbering options to allow interleaving of request and response messages at a packet boundary. Error recovery is improved by utilized new acknowledgement responses, SNAK provided for each new hole detected and RACK for each received packet after a SNAK. SNAK allows the indication of resource exhaustion at the receiver, causing entry into a recovery mode where only packets in a hole are transmitted until resources are recovered.Type: ApplicationFiled: March 14, 2024Publication date: September 19, 2024Inventors: Brian Hausauer, David Arditti Ilitzky, Linghe Wang
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Patent number: 11994615Abstract: Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.Type: GrantFiled: August 22, 2022Date of Patent: May 28, 2024Assignee: Intel CorporationInventors: Ignacio Alvarez, David Arditti Ilitzky, Patrick Andrew Mead, Javier Felip Leon, David Gonzalez Aguirre
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Publication number: 20240080050Abstract: Effective radio frequency interference (RFI) mitigation techniques are disclosed for use in wireless communication devices, among others. An RFI mitigation circuit may include a selector circuit to select between a cleaned signal and a clipped signal, and provide the selected signal as an output signal. The RFI mitigation circuit may also include a classifier circuit to generate a control input indication to the selector circuit to have the cleaned signal selected as the output signal based at least on a front-end circuit signal indicating that the front-end circuit is operating linearly and also indicating that the front-end circuit signal includes an interference signal. The classifier circuit may also generate the control input indication to have the clipped signal selected as the output signal based at least on the front-end circuit signal indicating that the front-end circuit is not operating linearly.Type: ApplicationFiled: November 8, 2023Publication date: March 7, 2024Inventors: David Arditti Ilitzky, Harry Skinner, Fernando Ramos Alarcon Barroso, Valeri Kontorovich Mazover, Rocio Hernandez Fabian
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Patent number: 11916800Abstract: Examples describe an egress port manager that uses an adaptive jitter selector to apply a jitter threshold level for a buffer, wherein the jitter threshold level is to indicate when egress of a packet segment from the buffer is allowed, wherein a packet segment comprises a packet header and wherein the jitter threshold level is adaptive based on a switch fabric load. In some examples, the jitter threshold level is to indicate a number of segments for the buffer's head of line (HOL) packet that are to be in the buffer or indicate a timer that starts at a time of issuance of a first read request for a first segment of the packet in the buffer. In some examples, the jitter threshold level is not more than a maximum transmission unit (MTU) size associated with the buffer.Type: GrantFiled: June 25, 2020Date of Patent: February 27, 2024Assignee: Intel CorporationInventors: David Arditti Ilitzky, John Greth, Robert Southworth, Karl S. Papadantonakis, Bongjin Jung, Arvind Srinivasan
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Patent number: 11848692Abstract: A signal processing device includes a prediction and correction engine configured to receive a signal including a target signal, and to execute a single-moment filter, based on a current measurement sample of the signal and a model of the target signal, to obtain a single-moment state estimate and a single-moment state estimate error covariance for the target signal, a covariance renormalizer configured to determine a multi-moment state estimate error covariance for the target signal based on a prior single-moment state estimate error covariance, corresponding to a sample prior to the current measurement sample, and the single-moment state estimate error covariance, and a multi-moment prediction and correction engine configured to execute a multi-moment filtering extension based on the current measurement sample and the multi-moment state estimate error covariance to obtain a multi-moment state estimate, and further configured to determine an estimate for the target signal based on the multi-moment state estiType: GrantFiled: September 28, 2017Date of Patent: December 19, 2023Assignee: Apple Inc.Inventors: David Arditti Ilitzky, Harry Skinner, Fernando Ramos Alarcon Barroso, Valeri Kontorovich Mazover, Rocio Hernandez Fabian
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Patent number: 11778573Abstract: Example predictive wireless feedback control systems disclosed herein include a receiver to receive measurements of a controlled system via a first wireless link. Disclosed example systems also include an observer to output estimated values of states of the controlled system based on a state space model that is updated based on the measurements. Disclosed example system further include a predictor to predict future values of the states of the controlled system based on the estimated values of the states, a first latency of the first wireless link and an upper limit of a second latency associated with a second wireless link that is to communicate values of a control signal to an actuator associated with the controlled system. In disclosed examples, the predictor is to output the predicted future values of the states to a controller that is to determine the control signal.Type: GrantFiled: September 20, 2021Date of Patent: October 3, 2023Assignee: Intel CorporationInventors: Linda Patricia Osuna Ibarra, David Gómez Gutiérrez, Dave Cavalcanti, David Arditti Ilitzky
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Patent number: 11722438Abstract: Examples describe a manner of scheduling packet segment fetches at a rate that is based on one or more of: a packet drop indication, packet drop rate, incast level, operation of queues in SAF or VCT mode, or fabric congestion level. Headers of packets can be fetched faster than payload or body portions of packets and processed prior to queueing of all body portions. In the event a header is identified as droppable, fetching of the associated body portions can be halted and any body portion that is queued can be discarded. Fetch overspeed can be applied for packet headers or body portions associated with packet headers that are approved for egress.Type: GrantFiled: August 21, 2019Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: John Greth, Arvind Srinivasan, Robert Southworth, David Arditti Ilitzky, Bongjin Jung, Gaspar Mora Porta
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Patent number: 11700209Abstract: Examples describe use of multiple meta-data delivery schemes to provide tags that describe packets to an egress port group. A tag, that is smaller than a packet, can be associated with a packet. The tag can be stored in a memory, as a group with other tags, and the tag can be delivered to a queue associated with an egress port. Packets received at an ingress port can be as non-interleaved to reduce underrun and providing cut-through to an egress port. A shared memory can be allocated to store packets received at a single ingress port or shared to store packets from multiple ingress ports.Type: GrantFiled: December 26, 2019Date of Patent: July 11, 2023Assignee: Intel CorporationInventors: Robert Southworth, Karl S. Papadantonakis, Mika Nystroem, Arvind Srinivasan, David Arditti Ilitzky, Jonathan Dama
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Publication number: 20230123665Abstract: Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.Type: ApplicationFiled: August 22, 2022Publication date: April 20, 2023Inventors: Ignacio ALVAREZ, David ARDITTI ILITZKY, Patrick Andrew MEAD, Javier FELIP LEON, David GONZALEZ AGUIRRE
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Patent number: 11551058Abstract: Example wireless feedback control systems disclosed herein include a receiver to receive a first measurement of a target system via a first wireless link. Disclosed example systems also include a neural network to predict a value of a state of the target system at a future time relative to a prior time associated with the first measurement, the neural network to predict the value of the state of the target system based on the first measurement and a prior sequence of values of a control signal previously generated to control the target system during a time interval between the prior time and the future time, and the neural network to output the predicted value of the state of the target system to a controller. Disclosed example systems further include a transmitter to transmit a new value of the control signal to the target system via a second wireless link.Type: GrantFiled: June 27, 2019Date of Patent: January 10, 2023Assignee: Intel CorporationInventors: David Gómez Gutiérrez, Linda Patricia Osuna Ibarra, Dave Cavalcanti, Leobardo Campos Macías, Rodrigo Aldana López, Humberto Caballero Barragan, David Arditti Ilitzky
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Patent number: 11474202Abstract: Apparatuses, methods and storage medium associated with compensating for a sensor deficiency in a heterogeneous sensor array are disclosed herein. In embodiments, an apparatus may include a compute device to aggregate perception data from individual perception pipelines, each of which is associated with respective one of different types of sensors of a heterogeneous sensor set, to identify a characteristic associated with a space to be monitored by the heterogeneous sensor set; detect a sensor deficiency associated with a first sensor of the sensors; and in response to a detection of the sensor deficiency, derive next perception data for more than one of the individual perception pipelines from sensor data originating from at least one second sensor of the sensors. Other embodiments may be disclosed or claimed.Type: GrantFiled: July 19, 2017Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: Ignacio Alvarez, David Arditti Ilitzky, Patrick Andrew Mead, Javier Felip Leon, David Gonzalez Aguirre
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Publication number: 20220271782Abstract: A signal processing device includes a prediction and correction engine configured to receive a signal including a target signal, and to execute a single-moment filter, based on a current measurement sample of the signal and a model of the target signal, to obtain a single-moment state estimate and a single-moment state estimate error covariance for the target signal, a covariance renormalizer configured to determine a multi-moment state estimate error covariance for the target signal based on a prior single-moment state estimate error covariance, corresponding to a sample prior to the current measurement sample, and the single-moment state estimate error covariance, and a multi-moment prediction and correction engine configured to execute a multi-moment filtering extension based on the current measurement sample and the multi-moment state estimate error covariance to obtain a multi-moment state estimate, and further configured to determine an estimate for the target signal based on the multi-moment state estiType: ApplicationFiled: September 28, 2017Publication date: August 25, 2022Inventors: David Arditti Ilitzky, Harry Skinner, Fernando Ramos Alarcon Barroso, Valeri Kontorovich Mazover, Rocio Hernandez Fabian
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Publication number: 20220217659Abstract: Example predictive wireless feedback control systems disclosed herein include a receiver to receive measurements of a controlled system via a first wireless link. Disclosed example systems also include an observer to output estimated values of states of the controlled system based on a state space model that is updated based on the measurements. Disclosed example system further include a predictor to predict future values of the states of the controlled system based on the estimated values of the states, a first latency of the first wireless link and an upper limit of a second latency associated with a second wireless link that is to communicate values of a control signal to an actuator associated with the controlled system. In disclosed examples, the predictor is to output the predicted future values of the states to a controller that is to determine the control signal.Type: ApplicationFiled: September 20, 2021Publication date: July 7, 2022Inventors: Linda Patricia Osuna Ibarra, David Gómez Gutiérrez, Dave Cavalcanti, David Arditti Ilitzky
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Patent number: 11320810Abstract: An apparatus for autonomous vehicles includes a perception pipeline having independent classification processes operating in parallel to respectively identify objects based on sensor data flows from multiple ones of a plurality of sensors. The apparatus also includes a sensor monitoring stage to operate in parallel with the perception pipeline and to use the sensor data flows to estimate and track a confidence level of each of the plurality of different sensors, and nullify a deficient sensor when the confidence level associated with the deficient sensor fails to meet a confidence threshold.Type: GrantFiled: September 28, 2017Date of Patent: May 3, 2022Assignee: Intel CorporationInventors: David Arditti Ilitzky, Ignacio J. Alvarez, Julio C. Zamora Esquivel, Paulo Lopez Meyer
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Publication number: 20220108045Abstract: Methods and apparatus relating to heterogeneous compute architecture hardware/software co-design for autonomous driving are described. In one embodiment, a heterogeneous compute architecture for autonomous driving systems (also interchangeably referred to herein as Heterogeneous Compute Architecture or “HCA” for short) integrates scalable heterogeneous processors, flexible networking, benchmarking tools, etc. to enable (e.g., system-level) designers to perform hardware and software co-design. With HCA system engineers can rapidly architect, benchmark, and/or evolve vehicle system architectures for autonomous driving. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: October 5, 2021Publication date: April 7, 2022Applicant: Intel CorporationInventors: Ignacio Alvarez, Patrick Mead, Carlos Ornelas, Daniel Lake, Miryam Lomeli Barajas, Victor Palacios Rivera, Yassir Mosleh, David Arditti Ilitzky, John Tell, Paul H. Dormitzer
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Patent number: 11237620Abstract: An apparatus is provided which comprises: a first Power Management Unit (PMU); and a second PMU, wherein the first PMU is to manage transition of the apparatus from a low power state to a first active state, wherein the second PMU is to manage transition of the apparatus from the first active state to a second active state, and wherein the second PMU is to be powered down while the apparatus is to be in the low power state.Type: GrantFiled: May 4, 2020Date of Patent: February 1, 2022Assignee: Intel CorporationInventors: Dileep J. Kurian, Pranjali S. Deshmukh, Sriram Kabisthalam Muthukumar, Ankit Gupta, Tanay Karnik, David Arditti Ilitzky, Saurabh Bhandari