Patents by Inventor David B. Glasco

David B. Glasco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7249224
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing remote data caches associated with the various clusters in the system. The remote data caches receive data and state information for memory lines held in remote clusters. If information for responding to a request is available in a remote data cache, a response with a completion indicator is provided to the requesting processor. The completion indicator allows the request to be met without having to probe local or remote nodes.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 24, 2007
    Assignee: Newisys, INc.
    Inventor: David B. Glasco
  • Patent number: 7162589
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for transmitting memory cancels to memory controllers in the various clusters of a multiple cluster system are provided. In one example, memory cancels are transmitted between clusters when it is determined that a memory line associated with a probe is dirty. The memory cancel directs the memory controller to no longer proceed with a data fetch from main memory. In another example, memory cancels are transmitted at a home cluster based on information in a coherence directory in order to more quickly end a data fetch.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: January 9, 2007
    Assignee: Newisys, Inc.
    Inventors: David B. Glasco, Rajesh Kota
  • Patent number: 7159137
    Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: January 2, 2007
    Assignee: Newisys, Inc.
    Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7117419
    Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: October 3, 2006
    Assignee: Newisys, Inc.
    Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7107408
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing can be performed before forwarding a data access request to a second cluster. The cache coherence controller can also forward the data access request to the second cluster before receiving a probe response.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: September 12, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 7107409
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing at a first cluster can be performed to improve overall transaction efficiency. Intervening requests from a second cluster can be handled using information from the speculative probe at the first cluster.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: September 12, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 7103726
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, memory controller filter information is used to probe a request or remote cluster while bypassing a home cluster memory controller.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: September 5, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 7103725
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in multiple processor, multiple cluster systems. A cache coherence controller associated with a first cluster of processors can determine whether speculative probing can be performed before forwarding a data access request to a second cluster. The cache coherence controller can send the data access request to the second cluster if the data access request can not be completed locally.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: September 5, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 7103823
    Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: September 5, 2006
    Assignee: Newisys, Inc.
    Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7103636
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or a home cluster. A speculative probe associated with a particular memory line is transmitted to the remote cluster before the cache access request associated with the memory line is serialized at a home cluster. When a non-speculative probe is received at a remote cluster, the information associated with the response to the speculative probe is used to provide a response to the non-speculative probe.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: September 5, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 7069392
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency and effectiveness of communications between multiprocessor clusters. Mechanisms for improving the accuracy of information available to an interconnection controller are implemented in order to allow the interconnection controller to increase reliability and reduce latency in a multiple cluster system. Protocol extensions and link layer extensions are provided with packets to convey information between interconnection controllers of separate multiprocessor clusters.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 27, 2006
    Assignee: Newisys, Inc.
    Inventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7047372
    Abstract: A computer system is described having a plurality of processing nodes interconnected by a first point-to-point architecture, and a system memory including a plurality of portions each of which is associated with one of the processing nodes. Each processing node includes a processor, and a memory controller for controlling access to the associated portion of the system memory, and may contain a host bridge for facilitating communication with a plurality of I/O devices. The first point-to-point architecture is operable to facilitate first transactions between the processors and the system memory. The computer system further includes at least one I/O controller and a second point-to-point architecture independent of the first point-to-point architecture and interconnecting the I/O controller and the host bridges. The at least one I/O controller is operable to facilitate second transactions between the I/O devices and the system memory via the second point-to-point architecture.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: May 16, 2006
    Assignee: Newisys, Inc.
    Inventors: Carl Zeitler, David B. Glasco, Rajesh Kota, Guru Prasadh, Richard R. Oehler, David S. Edrich
  • Patent number: 7024521
    Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster that are cached in remote clusters. Techniques are provided for managing eviction of entries in the cache coherence directory by locking memory lines in a home cluster without causing a memory controller to generate probes to processors in the home cluster.
    Type: Grant
    Filed: April 24, 2003
    Date of Patent: April 4, 2006
    Assignee: Newisys, INC
    Inventor: David B. Glasco
  • Patent number: 7003633
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, probe filter information is used to limit the number of probe requests transmitted to request and remote clusters.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: February 21, 2006
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 6950913
    Abstract: Methods and devices are provided for controlling lock and unlock operations within a computer system. A home cluster includes a home lock manager. The home lock manager is a master lock manager for the home cluster and for a plurality of remote clusters, the plurality of remote clusters including remote cache coherency controllers and a plurality of remote processors. Lock and unlock commands from the home lock manager are transmitted by a home cache coherency controller to the remote cache coherency controllers and forwarded to the remote processors.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: September 27, 2005
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Patent number: 6934814
    Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. An eviction manager is operable to designate one of the entries in the cache coherence directory to be evicted and maintain the designated entry in the cache coherence directory at least until a serialization point allows an eviction transaction corresponding to the designated entry to proceed.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: August 23, 2005
    Assignee: Newisys, Inc.
    Inventors: David B. Glasco, Rajesh Kota, Sridhar K. Valluru
  • Patent number: 6925536
    Abstract: Cache coherence directory eviction mechanisms are described for use in computer systems having a plurality of multiprocessor clusters. Interaction among the clusters is facilitated by a cache coherence controller in each cluster. A cache coherence directory is associated with each cache coherence controller identifying memory lines associated with the local cluster which are cached in remote clusters. The cache coherence controller is operable to initiate eviction of an entry in its directory corresponding to an unmodified copy of a memory line by sending a request to write to the memory line to a corresponding memory controller.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: August 2, 2005
    Assignee: Newisys, Inc.
    Inventors: David B. Glasco, Rajesh Kota, Sridhar K. Valluru
  • Patent number: 6865595
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Techniques are provided for speculatively probing a remote cluster from either a request cluster or a home cluster. A speculative probe associated with a particular memory line is transmitted to the remote cluster before the cache access request associated with the memory line is serialized at a home cluster. When a non-speculative probe is received at a remote cluster, the information associated with the response to the speculative probe is used to provide a response to the non-speculative probe.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: March 8, 2005
    Assignee: Newisys, Inc.
    Inventor: David B. Glasco
  • Publication number: 20040268052
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for reducing the number of transactions in a multiple cluster system are provided. In one example, owning node information is used to limit the number of probes transmitted in a particular cluster.
    Type: Application
    Filed: June 27, 2003
    Publication date: December 30, 2004
    Applicant: Newisys, Inc., A Delaware corporation
    Inventor: David B. Glasco
  • Publication number: 20040260832
    Abstract: Improved techniques are provided for reducing latency in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be encapsulated as inter-cluster packets and stored in a transmission buffer pending transmission on an inter-cluster link. When the transmission buffer is empty, a control character is transmitted on an inter-cluster link. The control character is not stored in the transmission buffer or in a reception buffer, but instead is dropped. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links, including the symbol(s) of the control character.
    Type: Application
    Filed: June 23, 2003
    Publication date: December 23, 2004
    Applicant: Newisys, Inc., A Delaware corporation
    Inventors: Rajesh Kota, Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco