Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1?M3; M1?M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1–M3; M1–M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: The method for powering down a circuit for a data retention mode includes: changing a supply voltage node from an active power voltage level to an inactive power level; coupling a source of a P channel device to the supply voltage node; providing a retaining power supply voltage level to a back gate of the P channel device; changing a drain voltage of the P channel device to a reference voltage level, wherein the reference voltage level is different from the retaining power supply voltage level; and changing a gate voltage of the P channel device to the reference voltage level.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped substrate (302) and an epitaxial layer (304) formed over the substrate (302). In one embodiment (200), a surrounding conductive structure (202) is formed on the peripheral edges of the semiconductor device (200) die. The surrounding conductive structure (202) is coupled to the substrate (302). In another embodiment, the back side of the die (404) is coupled to the conductive portion (402) of an integrated circuit package. The conductive portion (402) is coupled to a power supply voltage. In another embodiment (700), the surrounding conductive structure (702) is coupled to a power supply voltage by one or more bond pads (710) formed on, or coupled to, the surrounding conductive structure (702).

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1-M3; M1-M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M1−M3; M1−M4) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N10) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vt transistors (M1, M2, M5 and M6; M3, M4, M5 and M6) used to implement the state retention functionality.

Abstract: A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing a memory array column (30) including a plurality of memory cells (10). Each memory cell (10) includes drive transistors (12). A current limiting transistor (34) is coupled to the drive transistors (12). A mode signal (38) is coupled to the current limiting transistor (34). The mode signal (38) is operable to deactivate the current limiting transistor (34). The current limiting transistor (34) is deactivated when the mode signal (38) indicates that the memory array column (30) is in a standby mode.

Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (782) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (781) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (71a) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.

Abstract: A customized mattress evaluation system allows for uniquely designed mattresses based upon a particular customer's physical attributes. The system allows a retail mattress store to collect data from a sensor pad positioned on top of a support surface to generate a pressure profile for that person. The pressure profile and other information are used to generate specific mattress design parameters or co-efficients which are then utilized in designing a specific mattress uniquely customized for that person. Body type coefficients characteristic of an individual customer are correlated with coefficients developed for test persons for which various bedding products have been optimized. The optimization includes the rating of various bedding products for various body types by minimizing support pressures across the mattress and optimizing lumbar support for desired spinal curvature.

Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (722) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (721) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (72a1) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.

Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal.

Abstract: A method of forming a semiconductor circuit (20). The method forms a first transistor (NT1) using various steps, such as by forming a first source/drain region (361) as a first doped region in a fixed relationship to a semiconductor substrate (22) and forming a second source/drain region (362) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate (283) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST1) using various steps, such as by forming a third source/drain region (341) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region (342) as a fourth doped region in a fixed relationship to the semiconductor substrate.

Abstract: A method of forming a transistor (70) in a semiconductor active area (78). The method forms a gate structure (G2) in a fixed relationship to the semiconductor active area thereby defining a first source/drain region (R1) adjacent a first gate structure sidewall and a second source/drain region (R2) adjacent a second sidewall gate structure. The method also forms a lightly doped diffused region (801) formed in the first source/drain region and extending under the gate structure, wherein the lightly doped diffused region comprises a varying resistance in a direction parallel to the gate structure.

Abstract: A method is provided for reducing standby power in a memory array including a plurality of transistors. Each of the transistors includes a drain, a source and a gate. The method includes providing a memory array column (30) including a plurality of memory cells (10). Each memory cell (10) includes drive transistors (12). A current limiting transistor (34) is coupled to the drive transistors (12). A mode signal (38) is coupled to the current limiting transistor (34). The mode signal (38) is operable to deactivate the current limiting transistor (34). The current limiting transistor (34) is deactivated when the mode signal (38) indicates that the memory array column (30) is in a standby mode.

Abstract: A transistor (50) comprising a gate conductor (68) and a gate insulator (66) separating the gate conductor from a semiconductor material (64) having a first conductivity type. The transistor further comprises a drain region (722) having the first conductivity type. The transistor further comprises an angular implanted region (70) having a second conductivity type complementary of the first conductivity type and having an angular implanted region edge (70a) underlying the gate conductor, and the transistor includes a source region (721) formed at least in part within the angular implanted region. Finally, a transistor channel (74) is defined between an edge (72a1) of the source region proximate the gate conductor and the angular implanted region edge (70a) underlying the gate conductor.

Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.