Abstract: A circuit is designed with a decode circuit (313-315) having a first output terminal (319). The decode circuit is coupled to receive an address signal (81, 82, 85) having a first voltage range for producing a first output signal having one of a first and second logic levels. An output circuit (307, 309) is coupled to receive the first output signal and a power supply signal. The output circuit produces a second output signal having a second voltage range. A first latch transistor (301) is coupled to receive the second output signal. The first latch transistor is arranged to couple the first output terminal to a voltage terminal (209) in response to one of a first and second logic state of the second output signal. A second latch transistor (317) is coupled to receive the second output signal. The second latch transistor is arranged to couple the first output terminal to a reference terminal (318) in response to another of the first and second logic state of the second output signal.

Abstract: A compact data line arrangement (600) includes “twisted” data line pairs (604a-604c) disposed in a first direction. Each twisted data line pair (604a-604c) includes an upper segment pair (608a-608f) that is connected to a lower segment pair (610a-610f) by a twist structure (612a-612c). The upper and lower segment pairs (608a-608f and 610a-610f) can be formed with a first pitch using phase-shifted lithography. The twist structures (612a-612c) are formed from a second conductive layer, and have a greater pitch than the first pitch. The twist structures (612a-612c) are generally arranged in a second direction that is perpendicular to the first direction. Selected twist structures (612b) are offset in the first direction with respect to adjacent twist structures (612a and 612c). The offset twist structures (612a-612c) allow supplemental conductive lines (618) to be formed from the first conductive layer that extend in the first direction, between adjacent offset twist structures (612a and 612b).

Abstract: A hammer includes a rigid elongated support structure, a head carried at one end of the support structure, and a manually engageable gripping portion. An end of the elongated support structure includes a pair of vibration-receiving portions terminating in spaced apart relation with respect to each other and spaced from each other in a direction parallel to a swing plane of the hammer. The manually engageable gripping portion is formed from a resiliently deformable material molded around a portion of the support structure including the vibration-receiving portions so as to fill the space between the vibration-receiving portions. Vibration forces acting in a direction parallel to the swing plane of the hammer are generated by striking a striking surface of the head against an object.

Abstract: A dynamic random access memory (DRAM) includes a Y-select circuit (218) that connects a pair of bit lines (204a and 204b) to a pair of sense nodes (210a and 210b). The Y-select circuit (218) provides a first impedance in a read operation, and a second impedance that is lower than the first impedance, in a write operation. Changes in Y-select circuit (218) impedance are achieved by driving transistors (N210a and N210b) within the Y-select circuit (218) with a first voltage during a read operation, and a second voltage during a write operation.

Abstract: A random access memory (RAM) having a bipolar reduction in array operating voltage is disclosed. In a preferred embodiment, a clamping transfer gate circuit (414) couple pairs of bit lines (BL and /BL) to pairs of sense nodes (410 and 412). The clamping transfer gate circuit (414) includes an n-channel MOS transistor (N401 and N402) in series with a p-channel MOS transistor (P401 and P402) coupling a bit line (BL or /BL) to a sense node (410 or 412). The gates of the n-channel transistors (N401 and N402) are driven by the high power supply voltage (VDD), and the gates of the p-channel transistors (P401 and P402) are driven by the low power supply voltage (VSS). A sense amplifier circuit (418) drives the sense node pair (410 and 412) to opposite power supply voltages (VDD and VSS). The n-channel transistors (N401 and N402) in the clamping transfer gate circuit (414) clamp the voltage on the bit lines (BL and /BL) to a maximum level of VDD-Vtn, where Vtn is the n-channel transistor threshold voltage.

Abstract: An airbed having multi-zone air mattress is provided having a control that can identify the configuration of any of a plurality of hand control units connected thereto and can interpret control functions differently based on the identified unit configuration. A plurality of normally closed valves seal pressures in each of the zones when power to an air pump is off while mattress zone pressures are constantly monitored and the measurements sent by the control through a communications port for monitoring of the motion or care of a user of the bed and for analysis and diagnosis. When pump power is on, the pressure in the zones is regulated at predetermined pressure settings ideal for the user. Deviations from ideal pressure cause a programmed controller to calculate inflation or deflation times for the respective zones that would be required to inflate or exhaust the zones to the desired pressures.

Abstract: Quilts (120) are made from unquilted comforter bags (206) without premounting the panel on a rectangular frame (11,11a). A leading edge clamp (50,250) is preattached along the leading edge of a panel and fed from an operator station (15) onto a shuttle (20) movably mounted on the frame of a programmed single needle quilting machine (10,10a). Opposed belt conveyors (61,62) on opposite sides of the shuttle (20) advance the clamp (50,250) and pull the panel onto the shuttle (20), gripping the side edges of the panel as it is pulled. A trailing edge clamp bar (48) frictionally engages the panel as the panel is pulled onto the shuttle (20). The shuttle (20) reciprocates longitudinally under a sewing head (18) that moves transversely on the frame (11,11a) to stitch a pattern in the panel.

Abstract: A polysilicon resistor (40) includes a field oxide layer (12) and a polysilicon layer (20) that covers a portion of field oxide layer (12). The polysilicon layer (20) possesses a predetermined electrical resistance value. Nitride/oxide stack (42) covers a predetermined portion of the polysilicon layer (20) and forms at least one exposed location of polysilicon layer (20) on which not to implant a dopant to achieve a predetermined resistance value. Silicide layer (34) covers exposed location.

Abstract: The quilting of rectangular comforter bags, mattress cover panels or other similar panels is provided without the need to premount the panel on a rectangular frame. A leading edge clamp is preattached along the leading edge of a panel and the clamp is fed from an operator station to the upstream end of a shuttle movably mounted on the frame of a programmed single needle quilting machine. Opposed belt conveyors on opposite sides of the shuttle advance the clamp and pull the panel onto the shuttle, with the belts gripping the side edges of the panel as it is pulled. A trailing edge clamp bar frictionally engages the panel to provide trailing edge securement to the panel, with the belts and leading edge clamp providing securement around the other edges to stretch the panel on the shuttle. The shuttle reciprocates longitudinally under a sewing head that moves transversely on the frame at a quilting station, while the sewing head operates to stitch a pattern in the panel.

Abstract: Local reference voltage sub-circuits for ECL circuits are provided. The sub-circuits operate by a principal based on gating a current mirror. The sub-circuits described are superior to conventional approaches because less current is required during switching, better transfer characteristics are obtained and there exists, in some cases, less susceptibility to latch-up in comparison with conventional approaches.

Abstract: A quilting machine includes a multiple needle quilter with a panel cutter located in-line therewith and downstream thereof and having an accumulator therebetween. A programmable controller operates the quilter to stitch a programmed series of one or more patterns on a web. A feed roller angular encoder measures the quilted web length fed under tension to the accumulator. A detector signals when the accumulator is full, whereupon the controller causes web to be fed from the accumulator to the panel cutter, where it passes without tension thereon toward a photo sensor. The photo sensor signals the controller which activates the cutter to sever a predetermined panel length from the web. The controller then reads information from the encoder and the accumulator detector to determine the amount of stressed quilt required to replenish the cutoff panel length.

Abstract: A phase detector 10 is disclosed herein. A clock signal CLK (OR I), a marker signal MARK (or Q) and a data signal D are provided. The data signal may comprise a periodic clock signal. Sampler circuitry 50 receives the clock signal CLK, the marker signal MARK and the data signal D and generates a sampled clock signal and a sampled marker signal. Sign modifier circuitry 52 then receives the sampled clock signal and sampled marker signal and generates first and second command signals. Select circuitry 54 receiving these command signals selects a valid command signal based upon the data signal.

Abstract: A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

Abstract: A combination dynamic random access memory (DRAM) and static random access memory (SRAM) (150) array, includes a plurality of DRAM sense amplifiers (82, 84), each coupled to at least one DRAM bitline (86), with a plurality of DRAM memory cells selectively coupled to each of the bitlines (86). The sense amplifiers (82, 84) are organized into groups, with each group of sense amplifiers (82, 84), selectively coupled to respective true and complement I/O lines (102, 104). For each pair of the true and complement I/O lines (102, 104), an SRAM latch (150) is coupled to the pair.

Abstract: A method of reticle fabrication is disclosed which will reduce e-beam write time by two orders of magnitude for a 64 megabit DRAM. The method involves the mix of using both e-beam and optical lithography on a single reticle.

Abstract: The described embodiments of the present invention provide a bipolar transistor using an integrated field effect load device with one end of the load device integrally formed with the base of the transistor. The gate of the load device is connected to the emitter of the transistor. This structure is particularly advantageous in bipolar-complementary metal oxide semiconductor (BiCMOS) integrated circuitry. The unconnected end of the load device may be connected to the emitter using standard metal interconnection techniques or local interconnection techniques. In an additional embodiment of the invention, the end of the load device not connected to the base may be left unisolated to the substrate and thus connected to ground. It often occurs that the emitter of the bipolar transistor will be connected to ground and thus an automatic connection of the load device between the base and the emitter can be realized.

Abstract: The described embodiments of the present invention show a high voltage bipolar transistor integrated into a bipolar complementary metal oxide semiconductor integrated circuit. The high voltage transistor is fabricated using the available processing steps for fabricating other components in more standard BiCMOS processes. The collector of the transistor is formed using a buried N type region in a P substrate. A P well, rather than the conventional N well is formed above the buried N layer. The collector contact to the buried N layer is fabricated so as to surround the P well to provide a separate base region. A highly doped P type base region is formed with a P+ contact to this region. An N+ emitter is formed by out diffusion from a heavily doped polycrystalline silicon layer formed in contact with the base region.

Abstract: A bipolar/CMOS integrated circuit uses an on-chip amplifier to provide an intermediate voltage supply (18) to two groups of small geometry CMOS circuits. Bipolar devices (24) may use a full five volts from the outside supply rails (12, 14).

Abstract: The described embodiments of the present invention provide a structure and method for easily incorporating a high voltage lateral bipolar transistor in an integrated circuit. A buried base contact is formed and the base itself is formed of a well region in the integrated circuit. An oppositely doped well region is formed surrounding the collector region in the lateral PNP transistor. This collector well is formed of the opposite conductivity type of the base well. Contact to the collector and a heavily doped emitter are then formed in the collector well and base well, respectively. The more lightly doped collector well provides a thick depletion region between the collector and base and thus provides higher voltage operation. The positioning of the base/collector junction to the collector well at base well junction also reduces the spacing between the collector and the emitter.