Abstract: A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealing, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage.

Abstract: An output buffer (26) comprises a plurality of transistors (28) arranged in parallel between an output pin (34) and ground (38). Resistors (30) are connected in series between the drain (30) of the transistors (28) and the output pin (34) to ensure that an electrostatic discharge generated through normal handling will be distributed substantially equally through each of the transistors (28), thus preventing damage to the output buffer (26).

Abstract: A sensing and decoding scheme layout for a memory device comprising an array made up of columns and rows of memory cells is disclosed wherein sense amplifiers and pairs of memory cell columns are positioned so as to collectively fit within the pitches of the memory cells of the memory cell column pairs and where the sense amplifiers are connected in a one-to-one correspondence with columns of the memory cells.

Abstract: A knife of the kind having a blade (14, 43) and a handle has an extendible and retractable blade edge guard (16, 45). When the blade (14, 43) is extended, any violent movement of the knife with the cutting edge in a leading attitude acts inertially to disengage a detent (27, 55) from a recess (28, 57) in the guard (16, 45) so that a tension spring (17, 46) quickly extends the guard (16, 45) into its projecting, operative position to guard the blade edge (21, 50) and prevent at least serious injury. When the blade carrier (13, 42) is fully retracted, its engagement with a part (31, 58) of the guard (16, 45) causes that also to retract and be engaged again by the detent (27, 55) due to spring-bias.

Abstract: A process for forming N-channel MOS sources and drains, by implanting both phosphorus and arsenic. The high diffusivity of phosphorus causes it to diffuse in advance of the bulk of the arsenic, so that, after annealling, the source/drain regions have graded regions of gradually decreasing conductivity adjacent to the end of the channels. Thus the electric potential gradient at the ends of the channels is reduced, and impact ionization and hot carrier effects are avoided. The effective radius of the source (or drain) junction is increased, providing increased breakdown voltage.

Abstract: A method for forming CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anisotropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

Abstract: CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks.

Abstract: CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region.Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative doping effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.

Abstract: In the manufacture of a CMOS device, oxide is etched away from polysilicon gate-level interconnects, and from source or drain regions of either conductivity type to which the polysilicon gate-level interconnect is desired to be connected. A metal is then deposited, and silicide is formed to connect the gate-level interconnect to the respective source and drain regions. To ensure continuity of the silicide connection, the gate oxide beneath the gate level interconnect is slightly undercut by a wet etching process, additional polysilicon is deposited conformally overall, and the additional polysilicon is anistropically etched so that it is removed from all areas except those within the undercut region beneath the gate-level interconnect thus a continuous surface of silicon, from which a continuous layer of silicide is then grown, exists between the polysilicon gate-level interconnect and the respective source and drain regions. Thus, self-aligned contacts are created, and no unwanted pn junctions are created.

Abstract: An elongate substantially rectangular abrading tool blade, which can be used either for smoothing or for heavy stock removal, is formed of sheet metal and has a multiplicity of ground and hardened cutting teeth distributed over a cutting face of the blade and a multiplicity of associated through-the-blade apertures. The cutting teeth and associated apertures extend in several parallel rows across the blade at an angle other than perpendicular to the longitudinal axis of the blade, with several cutting teeth and associated apertures in each row, all the said cutting teeth facing the same way, namely, perpendicular to the said rows. Each said aperture is directly in front of and adjacent its associated cutting tooth relative to the direction in which the teeth face. Two longitudinal side edge portions of the blade are bent back through an acute angle relative to the cutting face from a longitudinal, substantially flat, middle portion of the blade.