Abstract: A method of implementing a processor architecture and corresponding system includes operands of a first size and a datapath of a second size. The second size is different from the first size. Given a first array of registers and a second array of registers, each register of the first and second arrays being of the second size, selecting a first register and corresponding second register from the first array and the second array, respectively, to perform operations of the first size. This allows a user, who is interfacing with the hardware processor through software, to provide data of the datapath bit-width instead of the register bit-width. Advantageously, the user is agnostic to the size of the registers.

Abstract: According to at least one example embodiment, a method and corresponding apparatus for controlling power in a multi-core processor chip include: accumulating, at a controller within the multi-core processor chip, one or more power estimates associated with multiple core processors within the multi-core processor chip. A global power threshold is determined based on a cumulative power estimate, the cumulative power estimate being determined based at least in part on the one or more power estimates accumulated. The controller causes power consumption at each of the core processors to be controlled based on the determined global power threshold. The controller may directly control power consumption at the core processors or may command the core processors to do so.

Abstract: A supercritical CO2 turbo-generator system includes multiple turbine generator units, a direct current bus, a plurality of active rectifiers, and a voltage controller. Each turbine generator unit includes a turbine with a supercritical CO2 input and a supercritical CO2 output, a generator with an electrical input and power output, a shaft connecting the turbine and generator, and a speed sensor for sensing shaft speed. The turbine generator units are connected in a cascading series with the input of a first turbine generator unit connected to a heated supercritical CO2 source and the input of each subsequent turbine generator unit is connected to the output of a prior turbine generator unit. The voltage controller monitors the speed sensor of the turbine generator units and varies the load on each generator to control shaft speed. Each active rectifier converts the power output of a generator to direct current, and the power from multiple active rectifiers is combined by the direct current bus.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Abstract: A system and corresponding method unwind instructions in an out-of-order (OoO) processor. The system comprises a mapper. In response to a restart event causing at least one instruction to be unwound, the mapper restores a present integer mapper state and present floating-point (FP) mapper state, used for mapping instructions, to a former integer mapper state and former FP mapper state, respectively. The mapper stores integer snapshots and FP snapshots of the present integer and FP mapper state, respectively, to expedite restoration to the former integer and FP mapper state, respectively. Access to the FP snapshots is blocked, intermittently, as a function of at least one FP present indicator used by the mapper to record presence of FP registers used as destinations in the instructions. Blocking the access, intermittently, improves power efficiency of the OoO processor.

Abstract: A system and corresponding method enforce strong load ordering in a processor. The system comprises an ordering ring that stores entries corresponding to in-flight memory instructions associated with a program order, scanning logic, and recovery logic. The scanning logic scans the ordering ring in response to execution or completion of a given load instruction of the in-flight memory instructions and detects an ordering violation in an event at least one entry of the entries indicates that a younger load instruction has completed and is associated with an invalidated cache line. In response to the ordering violation, the recovery logic allows the given load instruction to complete, flushes the younger load instruction, and restarts execution of the processor after the given load instruction in the program order, causing data returned by the given and younger load instructions to be returned consistent with execution according to the program order to satisfy strong load ordering.

Abstract: A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

Abstract: A system and corresponding method unwind instructions in an out-of-order (OoO) processor. The system comprises a mapper. In response to a restart event causing at least one instruction to be unwound, the mapper restores a present integer mapper state and present floating-point (FP) mapper state, used for mapping instructions, to a former integer mapper state and former FP mapper state, respectively. The mapper stores integer snapshots and FP snapshots of the present integer and FP mapper state, respectively, to expedite restoration to the former integer and FP mapper state, respectively. Access to the FP snapshots is blocked, intermittently, as a function of at least one FP present indicator used by the mapper to record presence of FP registers used as destinations in the instructions. Blocking the access, intermittently, improves power efficiency of the OoO processor.

Abstract: A system and corresponding method enforce strong load ordering in a processor. The system comprises an ordering ring that stores entries corresponding to in-flight memory instructions associated with a program order, scanning logic, and recovery logic. The scanning logic scans the ordering ring in response to execution or completion of a given load instruction of the in-flight memory instructions and detects an ordering violation in an event at least one entry of the entries indicates that a younger load instruction has completed and is associated with an invalidated cache line. In response to the ordering violation, the recovery logic allows the given load instruction to complete, flushes the younger load instruction, and restarts execution of the processor after the given load instruction in the program order, causing data returned by the given and younger load instructions to be returned consistent with execution according to the program order to satisfy strong load ordering.

Abstract: A system and corresponding method map instructions in an out-of-order (OoO) processor. The system comprises a mapper, integer snapshot circuitry, and floating-point (FP) snapshot circuitry. The mapper maps instructions by mapping integer and FP architectural registers (ARs) of the instructions to integer and FP physical registers of the OoO processor, respectively. The mapper records, via at least one present FP indicator, presence of FP ARs used as destinations in the instructions. The mapper copies, periodically, the integer mapper state to the integer snapshot circuitry and copies, intermittently, based on the at least one FP present indicator, the FP mapper state to the FP snapshot circuitry. Copies of the integer and FP mapper state in the integer and FP snapshot circuitry, respectively, improve performance for instruction unwinding caused, for example, by an exception, branch/jump mispredict, etc. By copying the FP mapper state, intermittently, power efficiency of the OoO processor is improved.

Abstract: The present disclosure describes technologies that permit sensitive detection of nucleic acids of interest (i.e., nucleic acids whose nucleotide sequence is or includes a target sequence). Among other things the disclosure provides a system comprising: a plurality of nucleic acid molecules having different nucleotide sequences; a set of ligation oligonucleotides, comprising: a first ligation oligonucleotide whose nucleotide sequence includes a templating element and a first target hybridization element; and a second ligation oligonucleotide whose nucleotide sequence includes a second target hybridization element and optionally a second templating element; wherein the target hybridization elements bind to different portions of a common target site, to form a gapped nucleic acid strand susceptible to ligation with a ligase to generate a ligated strand that is amenable to lateral flow assessment.

Abstract: An ultraviolet-curable (UV-curable) adhesive composition is disclosed. The adhesive composition comprises: A) an epoxy curing agent component; B) a microencapsulated epoxy resin component; C) an expansion agent component; D) a binder component; and E) a photoinitiator component. The adhesive composition is useful for forming an adhesive. In various embodiments, the adhesive composition is in the form of a stick. The adhesive composition is useful for securing a fastener (e.g. in a borehole).

Abstract: A mobile processing system is disclosed for the removal of radioactive contaminants from nuclear process wastewater. The system is fully scalable, modular, and portable allowing the system to be fully customizable according to site-specific remediation requirements. It is designed to be both transported and operated from standard sized intermodal containers or custom designed enclosures for increased mobility between sites and on-site, further increasing the speed and ease with which the system may be deployed. Additionally, the system is completely modular wherein the various modules perform different forms or stages of wastewater remediation and may be connected in parallel and/or in series. Depending on the needs of the site, one or more different processes may be used. In some embodiments, one or more of the same modules may be used in the same operation.

Abstract: A circuit and corresponding method enable mining for digital currency in a blockchain network. The circuit comprises a controller and at least one partial hash engine that (i) implements a hash function, partially, to compute a partial hash digest of a final hash digest for a block header of a block candidate and (ii) generates a notification based on determining that the partial hash digest satisfies a criterion. The controller includes a complete hash engine that implements the hash function, completely. In response to the notification generated, the controller activates the complete hash engine to compute, in its entirety, the final hash digest for the block header, effectuating a decision for submission of the block candidate with the block header to the blockchain network for mining the digital currency. Power savings and reduction in area are achieved relative to multiple hash engines that compute the entire final hash digest.

Abstract: A pressure relief assembly includes a housing defining an air passage chamber having at least one airflow opening. A flap is secured within the air passage chamber. The flap is configured to move into an open position to expose the airflow opening(s) to relieve air pressure. A cushion is secured to the housing underneath the flap. The cushion is configured to cushion motion of the flap. A first attachment securely couples the flap to the housing. A second attachment securely couples the cushion to the housing. The first attachment is separate and distinct from the second attachment.

Abstract: An illustrative aqueous ozone delivery device for use with an aqueous ozone generator cartridge can be used for body part, tissue, and instrument sanitizing, including hand rinsing, hand sanitizing, and clinical treatment. One embodiment includes a hooded sanitizing chamber and spray devices directed to each hand of a user, a docketing station for pluggably receiving a replaceable ozone generator and sensor cartridge, and a controller for sensing hand position and orientation, delivering a desired ozone concentration and duration.

Abstract: Embodiments of tuning fork-based sensors are disclosed. The sensors may include a measurement sensor that includes a diaphragm disposed on a proximal end and a plurality of forks extending from the diaphragm toward the distal end of the sensor. The diaphragm may have a domed geometry defining a curved surface. The plurality of forks may extending from the curved surface of the diaphragm toward the distal end and each of the plurality of forks may include a stub portion connected to the diaphragm, a stem portion, and a paddle portion. Some sensors, such as measurement sensors, may include a stem portion formed from a corrosive material. A reference sensor may be provided to compensate for changes in frequency measurements due to temperature, viscosity, or other environmental factors present in the environment where the sensors are deployed.

Abstract: An illustrative aqueous ozone sanitizing system for body part, tissue, and instrument sanitizing, including hand rinsing and sanitizing includes a sanitizing chamber, spray devices configured to simultaneously irrigate the entire left and right hand of a user, at least two aqueous ozone generators each fluidly coupled to a subset of the spray devices, and a housing for the sanitizing chamber having an opening for guiding the user's hand orientation and position into the sanitizing chamber.

Abstract: A merge unit configured to perform merge and permutation micro-operations by multiplexing data bytes of the inputs to simultaneously produce multiple data bytes of a merge and permutation result. Particularly, the merge unit includes a bank of MUXs arranged in parallel, each corresponding to one or more different data bytes in the merge result. When the merge unit is provided with a set of inputs, each MUX multiplexes the data bytes of the set of inputs (e.g., all the data bytes of the set of inputs) to selectively output a data byte to a particular location of the destination register storing the merge result. The selection by each MUX is individually controlled by a set of merge control words which identify a data byte location in an input and identify an input from the set of inputs.

Abstract: Systems and methods of selecting a collection of compatible issue-ready instructions for parallel execution by functional units in a superscalar processor in a single clock cycle. All possible instructions (opcodes) to be executed by the functional units are pre-arranged into several scenarios based on potential resource conflicts among the instructions. Each scenario includes multiple groups of predefined instructions. During operation, concurrently for all the groups, an issue-ready instruction is identified with reference to each group based on group-specific selection policies. Further, based on the identified instructions, predefined policies are applied to select one or more scenarios and select among the picks of the selected scenarios. As a result, the output instructions of the selected scenarios are issued for parallel execution by the functional units.