Patents by Inventor David Dzebisashvili

David Dzebisashvili has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock distribution module, synchronous digital system and method therefor
    Patent number: 9178730
    Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: November 3, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Priel, David Dzebisashvili, Leonid Fleshel
  • CLOCK DISTRIBUTION MODULE, SYNCHRONOUS DIGITAL SYSTEM AND METHOD THEREFOR
    Publication number: 20150098540
    Abstract: A clock distribution module for a digital synchronous system is described. The clock distribution module comprising a first node arranged to comprise a clock signal comprising a propagation delay relative to a reference clock signal, at least one further node arranged to comprise a clock signal comprising a propagation delay relative to the reference clock signal corresponding to that of the first node, and a clock configuration module. The clock configuration module is arranged to receive at least one indication of clock skew between the first node and at least one further node of the clock distribution module, and to selectively couple the first node to the at least one further node based at least partly on the at least one indication of clock skew there between.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 9, 2015
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Michael Priel, David Dzebisashvili, Leonid Fleshel