Patents by Inventor David E. Reed

David E. Reed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6115198
    Abstract: A partial response class-IV (PR4) sampled amplitude read channel is disclosed for detecting user data and embedded servo data. The detected servo data is encoded using a novel servo code capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In one embodiment, the servo code corrects certain minimum distance error events, such as a bit shift error event, associated with a trellis type sequence detector. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits relative to the minimum distance error events corrected.
    Type: Grant
    Filed: October 29, 1997
    Date of Patent: September 5, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss
  • Patent number: 6108151
    Abstract: A sampled amplitude read channel is disclosed for reading data recorded on a disk storage medium by detecting an estimated binary sequence from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a read head positioned over the disk storage medium. The read channel comprises a sampling device, such as an analog-to-digital converter (A/D), for sampling the analog read signal to generate the discrete time sample values and for sampling at least one other auxillary analog input signal, such as a servo control signal. In this manner, performance characteristics of the read channel can be measured, such as the driving current applied to the servo control voice coil motor (VCM), without requiring additional hardware.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: August 22, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: Tyson Tuttle, Diwakar Vishakhadatta, Jerrel P. Hein, David R. Welland, David E. Reed, Richard T. Behrens, William G. Bliss, Paul M. Romano, Trent O. Dudley, Christopher P. Zook
  • Patent number: 6078444
    Abstract: A circuit is provided for use with analog to digital conversion techniques in sampled amplitude read channel integrated circuits. A common ADC may be utilized for conversion of both high frequency disk data such as user data and servo data, for example, and for low frequency auxiliary data such as, for example, motor back-EMF current signals. The ADC may utilize the relatively low bit accuracy required for the read channel disk data and through oversampling techniques obtain sufficient conversion accuracy to meet the relatively higher precision requirements for the auxiliary data conversion. The auxiliary data is modified by a ramp signal and the ADC is run on a clock generated from a dithered frequency source so that ADC quantization errors may be randomized.
    Type: Grant
    Filed: April 18, 1996
    Date of Patent: June 20, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: G. Diwakar Vishakhadatta, David E. Reed, Jerrell P. Hein, G. Tyson Tuttle
  • Patent number: 6052248
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems employing a run-length limited (RLL) d=1 channel code which compensates for partial erasure, and a parity channel code for enhancing the operation of a remod/demod sequence detector. During a write operation, after encoding the user data into codewords comprising the RLL d=1 constraint, the parity over one interleave of a block of NRZI bits is computed and two parity bits appended to form a parity codeword. For an even number of "1" bits in the block, the parity bits are set to "00". For an odd number of "1" bits in the block, the parity bits are set to "10" if the codeword ends with a "0" bit and to "01" if the codeword ends with a "1" bit, thereby maintaining the RLL d=1 constraint. Thus, a parity codeword will always comprise an even number of "1" bits (even parity).
    Type: Grant
    Filed: January 30, 1998
    Date of Patent: April 18, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss
  • Patent number: 6038091
    Abstract: A thermal asperity-tolerant read channel is provided for a magnetic disk drive. Thermal asperities are detected by a digital detector which includes a pre-filter, a first threshold comparator and, optionally, a second threshold comparator. The pre-filter reduces noise and signal variation in the analog-to-digital converter output to enable better detection of a DC shift caused by a thermal asperity. The first threshold comparator compares the pre-filter output to a predetermined level; if the predetermined level is exceeded, the comparator output is set to one state, providing an initial indication of the presence of a thermal asperity. The optional second threshold comparator determines whether, out of a predetermined number of comparator outputs, the number in the one state exceeds programmed value; if so, the second threshold comparator outputs a final indication of the presence of a thermal asperity.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: March 14, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, German S. Feyh
  • Patent number: 6028728
    Abstract: A sub-baud rate write circuit is disclosed which writes RLL encoded channel data to a disk storage medium using a write clock frequency significantly below the baud rate. This allows for a higher channel data rate without increasing the cost and complexity of the write circuitry. The write circuitry operates by re-encoding the RLL encoded channel data according to a particular mapping to generate write data at the write clock rate, and then writing the write data to the disk at appropriate phase delays. The phase delays are generated by passing the write clock through an array of delay circuits. The resulting write signal is the same as if the RLL encoded data were written to the disk using a baud rate write clock. The write circuitry of the present invention is ideally suited for use in a sub-sampled read/write channel where the object is to reduce the cost and complexity by clocking the entire channel at a frequency significantly below the baud rate.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: February 22, 2000
    Assignee: Cirrus Logic, Inc.
    Inventor: David E. Reed
  • Patent number: 6023386
    Abstract: In a magnetic disk storage system, a sampled amplitude read channel is disclosed that employs a fault tolerant sync mark detector for detecting a sync mark from the channel samples in order to synchronize a time varying sequence detector. The read channel preferably employs PR4 equalization for timing recovery and gain control, and EEPR4 equalization for sequence detection. The EEPR4 sequence detector operates according to a time varying state machine matched to a predetermined trellis code constraint. Because the state machine is time varying, the data stream must be synchronized at the input of the sequence detector rather than at the output as in the prior art. The present invention provides a fault tolerant sync mark detector that detects a sync mark from the EEPR4 channel samples before being input into the sequence detector.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: February 8, 2000
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss
  • Patent number: 6005727
    Abstract: A servo decoder is disclosed for disc storage systems that operates according to a novel coding scheme capable of accurately decoding detected codewords representing servo track address during seek operations, even when the recording head flies between two adjacent tracks, and capable of correcting errors in the detected codedwords caused by noise in the read signal, such as inter-symbol interference. In a first embodiment, the coding scheme comprises an error correcting code (ECC) capable of correcting a predetermined number of bit errors in the detected codewords. To achieve the equivalent effect of a conventional Gray code, the codewords are arranged such that adjacent track addresses differ by a number of bits equal to the minimum distance of the ECC code. In a second embodiment, the servo code corrects certain minimum distance error events associated with a trellis type sequence detector.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: December 21, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: Richard T. Behrens, Christopher P. Zook, David E. Reed, Stephen A. Turk
  • Patent number: 5966415
    Abstract: A sampled amplitude read channel for disk storage systems is disclosed which asynchronously sub-samples an analog read signal significantly below the Nyquist rate (the baud rate) in order to increase the effective data rate without increasing the frequency of the sampling device. Interpolated timing recovery up-samples the asynchronous samples to generate sample values synchronized to the baud rate, and a Viterbi sequence detector detects the recorded digital data from the synchronous sample values. To compensate for the time-varying characteristics of the recording device, a discrete-time equalizer adaptively equalizes the asynchronous sample values using a least mean square (LMS) adaptive algorithm,W.sub.k+1 =W.sub.k -.mu..multidot.e.sub.k .multidot.X.sub.k,where W.sub.k is a vector of FIR filter coefficients, .mu. is a programmable gain, e.sub.k is a sample error between the FIR filter's actual output and a desired output, and X.sub.k is a vector of samples values from the FIR filter input.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: October 12, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: William G. Bliss, Sian She, David E. Reed
  • Patent number: 5961658
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: October 5, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, Lisa C. Sundell
  • Patent number: 5926490
    Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs a remod/demod sequence detector guided by an error syndrome of an error detection code (EDC). The remod/demod sequence detector comprises: a conventional trellis type maximum likelihood sequence detector, such as a Viterbi detector, for detecting a preliminary binary sequence from the channel sample values; a syndrome generator for generating an error syndrome in response to the preliminary binary sequence; a remodulator for remodulating the detected binary sequence into a sequence of estimated ideal sample values; a sample error generator for subtracting the channel samples from the estimated samples to generate a sample error sequence; an error pattern detector for detecting potential error events in the sample error sequence; and an error corrector for correcting the preliminary binary sequence when the error syndrome indicates that an error occurred.
    Type: Grant
    Filed: May 23, 1997
    Date of Patent: July 20, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss, Lisa C. Sundell
  • Patent number: 5862161
    Abstract: This invention provides apparatus for reliably and efficiently reading data from a magnetic storage medium under the condition that adjacent magnetization regions are partially erased. A simplified nonlinear description of a read signal resulting from such partially erased magnetization regions is used to derive a state machine model of the read signal. The state machine model implicitly defines a sequence detector for demodulating recorded data from received samples. For a PR4 signal, the state machine has ten states; for an EPR4 signal, the state machine has eighteen states; and for an EEPR4 signal, the state machine has twenty-six states. The PR4 machine is further simplified using squaring and state sharing to provide state machine models with six and four states.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: January 19, 1999
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, Richard T. Behrens
  • Patent number: 5854714
    Abstract: A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: December 29, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss
  • Patent number: 5802118
    Abstract: A sampled amplitude read channel is disclosed for reading binary data from a computer disk storage system, wherein the read channel sub-samples an analog read signal at a rate lower than the baud rate and detects the binary data from the sub-sampled values using a sequence detector. In one embodiment, the sub-sampled values are interpolated to generate synchronous sample values which are processed by a conventional sequence detector. In another embodiment, the sequence detector is modified to detect the binary data directly from the sub-sampled values. In yet another embodiment, the sequence detector comprises a remodulator and an error pattern detector for detecting and correcting bit errors in the detected binary data. In addition, for the various embodiments a channel code increases the distance property of the sequence detector in order to compensate for the degradation in performance caused by sub-sampling.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: September 1, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: William G. Bliss, David E. Reed, Richard T. Behrens
  • Patent number: 5796535
    Abstract: A sampled amplitude read channel incorporated within a magnetic disk storage system for reading data recorded in concentric tracks on a magnetic medium, where the data comprises user data sectors recorded at varying data rates across a plurality of predefined zones and embedded servo data sectors recorded at the same data rate across the zones. The sampled amplitude read channel comprises a timing recovery component for synchronous sampling of a read signal from a magnetic read head positioned over the magnetic medium, a gain control component for adjusting the amplitude of the read signal, and a DC offset component for cancelling a DC offset in the read signal. These components are dynamically configured to operate according to whether the read channel is processing user data or embedded servo data.
    Type: Grant
    Filed: May 12, 1995
    Date of Patent: August 18, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: Tyson Tuttle, Diwakar Vishakhadatta, Jerrel P. Hein, David R. Welland, David E. Reed, Richard T. Behrens, William G. Bliss, Paul M. Romano, Trent O. Dudley, Christopher P. Zook
  • Patent number: 5786950
    Abstract: A PR4 sampled amplitude read channel is disclosed which employs an NRZI modulator for writing encoded user data directly to a magnetic disc storage medium instead of using a conventional 1/(1+D.sup.2) precoder. This avoids the ambiguous initial state of the precoder and allows the read channel to directly control the magnetic flux transitions written onto the disc. Upon read back, a PR4 sequence detector outputs a preliminary data sequence which is converted back into the NRZI domain and then decoded into an estimated user data sequence.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: July 28, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: Christopher P. Zook, David E. Reed
  • Patent number: 5771127
    Abstract: In a computer disk storage system for recording binary data, a sampled amplitude read channel comprises a sampling device for asynchronously sampling pulses in an analog read signal from a read head positioned over a disk storage medium, interpolated timing recovery for generating synchronous sample values, and a sequence detector for detecting the binary data from the synchronous sample values. The sequence detector comprises a demodulator for detecting a preliminary binary sequence which may contain bit errors, a remodulator for remodulating to estimated sample values, a means for generating sample error values, an error pattern detector for detecting the bit errors, an error detection validator, and an error corrector for correcting the bit errors. The remodulator comprises a partial erasure circuit which compensates for the non-linear reduction in amplitude of a primary pulse caused by secondary pulses located near the primary pulse.
    Type: Grant
    Filed: July 29, 1996
    Date of Patent: June 23, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William R. Foland, Jr., William G. Bliss, Richard T. Behrens, Lisa C. Sundell
  • Patent number: 5726818
    Abstract: A sampled amplitude read channel reads user data and embedded servo data stored on a magnetic medium by detecting digital data from a sequence of discrete time interpolated sample values. A write frequency synthesizer generates a write clock for writing digital data to the magnetic medium at a predetermined baud rate for a selected zone, and upon read back, a read frequency synthesizer generates a fixed sampling clock at a frequency slightly higher than the write frequency at the outer zone. A sampling device samples the analog read signal at this fixed sampling rate across the data zones and servo wedges to generate a sequence of discrete time channel samples that are not synchronized to the baud rate. Before sampling, an analog receive filter processes the read signal to attenuate aliasing noise without having to adjust its spectrum across data zones or servo wedges. A discrete time equalizing filter equalizes the channel samples according to a predetermined partial response (PR4, EPR4, EEPR4, etc.).
    Type: Grant
    Filed: December 5, 1995
    Date of Patent: March 10, 1998
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, William G. Bliss
  • Patent number: 5668678
    Abstract: A discrete time servo demodulation technique incorporated within a sampled amplitude read channel to demodulate embedded servo field information stored on a magnetic medium. The servo field information is transduced by a read head into an analog signal, and converted to a sequence of sample values in the read channel. The demodulation technique is responsive to the sample values and includes a discrete time peak detector for detecting servo data, and a discrete time servo burst amplitude detector for measuring the amplitude of servo bursts. Peaks are detected in the analog read signal by sensing a change of slope from the sequence of sample values. The peaks are qualified by polarity in that a peak is detected only if its polarity is opposite in sign from the previous peak. The servo burst amplitudes are measured by interpolating, rectifying, and accumulating the sequence of sample values corresponding to the servo bursts.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: September 16, 1997
    Assignee: Cirrus Logic, Inc.
    Inventors: David E. Reed, Richard T. Beherns, William G. Bliss
  • Patent number: 4493825
    Abstract: Purified antigenically selective vaccines for domestic animals are prepared from microorganism cultures containing the immunizing agent by first complexing the immunizing agent with micro-particles having bound IgG antibodies specific for the immunizing agent, separating the resulting complex, and preparing a vaccine directly therefrom containing the antigen-antibody complex. The micro-particles preferably have Protein A in their outer surfaces for binding to the specific antibodies. The complex-containing vaccines provide effective immunization. The method and the resulting vaccines are particularly useful in preparing viral and bacterial subunit vaccines.
    Type: Grant
    Filed: October 5, 1982
    Date of Patent: January 15, 1985
    Assignee: Iowa State University Research Foundation
    Inventors: Kenneth B. Platt, David E. Reed