Patents by Inventor David F. Abdo
David F. Abdo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10637400Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.Type: GrantFiled: September 5, 2018Date of Patent: April 28, 2020Assignee: NXP USA, Inc.Inventors: Jeffrey K. Jones, David F. Abdo, Basim H. Noori
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Patent number: 10630246Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.Type: GrantFiled: October 9, 2017Date of Patent: April 21, 2020Assignee: NXP USA, Inc.Inventors: David F. Abdo, Jeffrey K. Jones
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Publication number: 20190020314Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.Type: ApplicationFiled: September 5, 2018Publication date: January 17, 2019Inventors: JEFFREY K. JONES, DAVID F. ABDO, BASIM H. NOORI
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Patent number: 10109594Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.Type: GrantFiled: April 22, 2016Date of Patent: October 23, 2018Assignee: NXP USA, INC.Inventors: Lakshminarayan Viswanathan, Michael E. Watts, David F. Abdo
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Patent number: 10075132Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.Type: GrantFiled: March 24, 2015Date of Patent: September 11, 2018Assignee: NXP USA, INC.Inventors: Jeffrey K. Jones, David F. Abdo, Basim H. Noori
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Patent number: 9893027Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.Type: GrantFiled: April 7, 2016Date of Patent: February 13, 2018Assignee: NXP USA, INC.Inventors: David F. Abdo, Sivanesan A/L Sathiapalan
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Publication number: 20180034421Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Inventors: David F. ABDO, Jeffrey K. JONES
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Publication number: 20180012855Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.Type: ApplicationFiled: September 6, 2017Publication date: January 11, 2018Inventors: David F. Abdo, Sivanesan A/L Sathiapalan
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Publication number: 20170294393Abstract: A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.Type: ApplicationFiled: April 7, 2016Publication date: October 12, 2017Inventors: David F. Abdo, Sivanesan A/L Sathiapalan
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Patent number: 9787254Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.Type: GrantFiled: September 23, 2015Date of Patent: October 10, 2017Assignee: NXP USA, INC.Inventors: David F. Abdo, Jeffrey K. Jones
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Publication number: 20170085228Abstract: Embodiments include packaged semiconductor devices and methods of manufacturing packaged semiconductor devices. A semiconductor die includes a conductive feature coupled to a bottom surface of the die. The conductive feature only partially covers the bottom die surface to define a conductor-less region that spans a portion of the bottom die surface. The die is encapsulated by attaching the encapsulant material to the bottom die surface (e.g., including over the conductor-less region). The encapsulant material includes an opening that exposes the conductive feature. After encapsulating the die, a heatsink is positioned within the opening, and a surface of the heatsink is attached to the conductive feature. Because the heatsink is attached after encapsulating the die, the heatsink sidewalls are not directly bonded to the encapsulant material.Type: ApplicationFiled: September 23, 2015Publication date: March 23, 2017Inventors: DAVID F. ABDO, JEFFREY K. JONES
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Publication number: 20160285418Abstract: An amplifier includes a semiconductor substrate. A first conductive feature partially covers the bottom substrate surface to define a conductor-less region of the bottom substrate surface. A first current conducting terminal of a transistor is electrically coupled to the first conductive feature. Second and third conductive features may be coupled to other regions of the bottom substrate surface. A first filter circuit includes an inductor formed over a portion of the top substrate surface that is directly opposite the conductor-less region. The first filter circuit may be electrically coupled between a second current conducting terminal of the transistor and the second conductive feature. A second filter circuit may be electrically coupled between a control terminal of the transistor and the third conductive feature. Conductive leads may be coupled to the second and third conductive features, or the second and third conductive features may be coupled to a printed circuit board.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Inventors: JEFFREY K. JONES, DAVID F. ABDO, BASIM H. NOORI
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Patent number: 9425161Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: GrantFiled: July 24, 2015Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
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Publication number: 20160240488Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.Type: ApplicationFiled: April 22, 2016Publication date: August 18, 2016Inventors: Lakshminarayn Viswanathan, Michael E. Watts, David F. Abdo
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Patent number: 9349693Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.Type: GrantFiled: August 5, 2014Date of Patent: May 24, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Viswanathan Lakshminarayan, Michael E. Watts, David F. Abdo
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Publication number: 20160043039Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.Type: ApplicationFiled: August 5, 2014Publication date: February 11, 2016Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Viswanathan Lakshminarayan, Michael E. Watts, David F. Abdo
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Publication number: 20150333031Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: ApplicationFiled: July 24, 2015Publication date: November 19, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. MAHALINGAM, DAVID F. ABDO, JAYNAL A. MOLLA
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Patent number: 9111984Abstract: The embodiments described herein provide an apparatus and method for separating dies from adhesive tape. In general, these techniques use applied vacuum and one or more channels in an extractor base surface to progressively peel adhesive tape away from the die. When the adhesive tape has been peeled away from the entire die the die can be removed and packaged. Such a technique can reduce the strain the die and thus may reduce the probability of cracks occurring in the die, and is thus particularly applicable to removing adhesive tape from relatively thin dies.Type: GrantFiled: October 28, 2013Date of Patent: August 18, 2015Assignee: FREESCALE SEMICONDUCTOR INC.Inventors: Audel A. Sanchez, David F. Abdo, Michael L. Eleff
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Patent number: 9099567Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: GrantFiled: November 25, 2013Date of Patent: August 4, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Lakshminarayan Viswanathan, L. M. Mahalingam, David F. Abdo, Jaynal A. Molla
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Publication number: 20150146399Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.Type: ApplicationFiled: November 25, 2013Publication date: May 28, 2015Inventors: LAKSHMINARAYAN VISWANATHAN, L.M. Mahalingam, David F. Abdo, Jaynal A. Molla