Patents by Inventor David F. Seefeldt

David F. Seefeldt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Hierarchical variable die size gate array architecture
    Patent number: 4978633
    Abstract: A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern.
    Type: Grant
    Filed: August 22, 1989
    Date of Patent: December 18, 1990
    Assignee: Harris Corporation
    Inventors: David F. Seefeldt, Michael J. Iacoponi, David K. Vail, Jr.
  • Hierarchical variable die size gate array architecture
    Patent number: 4864381
    Abstract: A variable die size gate array architecture is realizable by forming in a semiconductor substrate an array of circuit devices separated from one another by a network of routing channels. Through the selective interconnection of the routing channels and the circuit devices a prescribed signal processing function may be implemented. The array of circuit devices includes gate supercells each of which is configurable to perform a respective signal processing operation, and input/output supercells each of which is configurable to effectively perform input/output interfacing between the gate supercells and signal terminals external to the array. The gate supercells and the input/output supercells are intermingled with one another in the array in accordance with a prescribed two-dimensional distribution pattern.
    Type: Grant
    Filed: December 19, 1988
    Date of Patent: September 5, 1989
    Assignee: Harris Corporation
    Inventors: David F. Seefeldt, Michael J. Iacoponi, David K. Vail, Jr.