Patents by Inventor David Gani

David Gani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069667
    Abstract: Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer, forming an interconnect structure of through-silicon vias within the substrate, and singulating the bonded wafers to yield individually packaged sensors. The wafer level proximity sensor is smaller than a conventional proximity sensor and can be manufactured using a shorter fabrication process at a lower cost. The proximity sensors are coupled to external components by a signal path that includes the through-silicon vias and a ball grid array formed on a lower surface of the silicon substrate. The design of the wafer level proximity sensor passes more light from the light emitter and more light to the light sensor.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 20, 2021
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: David Gani
  • Publication number: 20210202419
    Abstract: The present disclosure is directed to a wafer level chip scale package (WLCSP) with various combinations of contacts and Under Bump Metallizations (UBMs) having different structures and different amounts solder coupled to the contacts and UBMs. Although the contacts have different structures and the volume of solder differs, the total standoff height along the WLCSP remains substantially the same. Each portion of solder coupled to each respective contact and UBM includes a point furthest away from an active surface of a die of the WLCSP. Each point of each respective portion of solder is co-planar with each other respective point of the other respective portions of solder. Additionally, the contacts with various and different structures are positioned accordingly on the active surface of the die of the WLCSP to reduce failures that may result from the WLCSP being exposed to thermal cycling or the WLCSP being dropped.
    Type: Application
    Filed: November 25, 2020
    Publication date: July 1, 2021
    Inventor: David GANI
  • Publication number: 20210159136
    Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Inventors: Yun LIU, David GANI
  • Publication number: 20210066198
    Abstract: The present disclosure is directed to a package that includes openings that extend into the package. The openings are filled with a conductive material to electrically couple a first die in the package to a second die in the package. The conductive material that fills the openings forms electrical interconnection bridges between the first die and the second die. The openings in the package may be formed using a laser and a non-doped molding compound, a doped molding compound, or a combination of doped or non-doped molding compounds.
    Type: Application
    Filed: August 6, 2020
    Publication date: March 4, 2021
    Inventors: Yong CHEN, David GANI
  • Publication number: 20210035952
    Abstract: A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.
    Type: Application
    Filed: July 21, 2020
    Publication date: February 4, 2021
    Inventors: Yong CHEN, David GANI
  • Patent number: 10910287
    Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 2, 2021
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yun Liu, David Gani
  • Publication number: 20210020555
    Abstract: The present disclosure provides devices and methods in which a semiconductor chip has a reduced size and thickness. The device is manufactured by utilizing a sacrificial or dummy silicon wafer. A recess is formed in the dummy silicon wafer where the semiconductor chip is mounted in the recess. The space between the dummy silicon wafer and the chip is filled with underfill material. The dummy silicon wafer and the backside of the chip are etched using any suitable etching process until the dummy silicon wafer is removed, and the thickness of the chip is reduced. With this process, the overall thickness of the semiconductor chip can be thinned down to less than 50 ?m in some embodiments. The ultra-thin semiconductor chip can be incorporated in manufacturing flexible/rollable display panels, foldable mobile devices, wearable displays, or any other electrical or electronic devices.
    Type: Application
    Filed: July 13, 2020
    Publication date: January 21, 2021
    Inventors: Laurent HERARD, David PARKER, David GANI
  • Publication number: 20200365492
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Application
    Filed: July 31, 2020
    Publication date: November 19, 2020
    Inventors: Rennier RODRIGUEZ, Bryan Christian BACQUIAN, Maiden Grace MAMING, David GANI
  • Patent number: 10763194
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 1, 2020
    Assignees: STMICROELECTRONICS, INC., STMICROELECTRONICS PTE LTD
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20200241068
    Abstract: A method of testing integrated circuit die for presence of a crack includes performing back end integrated circuit fabrication processes on a wafer having a plurality of integrated circuit die, the back end fabrication including an assembly process. The assembly process includes a) lowering a tip of a first manipulator arm to contact a given die such that pogo pins extending from the tip make electrical contact with conductive areas on the given die so that the pogo pins are electrically connected to a crack detector on the given die, b) picking up the given die using the first manipulator arm, and c) performing a conductivity test on the crack detector using the pogo pins to determine presence of a crack in the given die that extends from a periphery of the die, through a die seal ring of the die, and into an integrated circuit region of the die.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 30, 2020
    Applicant: STMicroelectronics Pte Ltd
    Inventors: Pedro Jr Santos PERALTA, David GANI
  • Publication number: 20200168582
    Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.
    Type: Application
    Filed: November 22, 2019
    Publication date: May 28, 2020
    Applicants: STMicroelectronics Pte Ltd, STMicroelectronics (Grenoble 2) SAS
    Inventors: David GANI, Jean-Michel RIVIERE
  • Publication number: 20190361093
    Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.
    Type: Application
    Filed: August 13, 2019
    Publication date: November 28, 2019
    Inventor: David GANI
  • Publication number: 20190319157
    Abstract: A carrier wafer has a back face and a front face and a network of electrical connections between the back face and the front face. A first electronic chip is mounted with its bottom face on top of the front face of the carrier wafer. The first electronic chip has a through-opening extending between the bottom face and a face. A second electronic chip is installed in the through-opening and mounted to the front face of the carrier wafer.
    Type: Application
    Filed: April 8, 2019
    Publication date: October 17, 2019
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics Pte Ltd
    Inventors: Romain COFFY, Laurent HERARD, David GANI
  • Patent number: 10422860
    Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 24, 2019
    Assignee: STMicroelectronics Pte Ltd
    Inventor: David Gani
  • Publication number: 20190267302
    Abstract: A semiconductor package having a die with a sidewall protected by molding compound, and methods of forming the same are disclosed. The package includes a die with a first surface opposite a second surface and sidewalls extending between the first and second surfaces. A redistribution layer is formed on the first surface of each die. An area of the first surface of the die is greater than an area of the redistribution layer, such that a portion of the first surface of the die is exposed. When molding compound is formed over the die and the redistribution layer to form a semiconductor package, the molding compound is on the first surface of the die between an outer edge of the redistribution layer and an outer edge of the first surface. The molding compound is also on the sidewalls of the die, which provides protection against chipping or cracking during transport.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 29, 2019
    Inventors: Yun LIU, David GANI
  • Publication number: 20190195685
    Abstract: One or more embodiments are directed to ambient light sensor packages, and methods of making ambient light sensor packages. One embodiment is directed to an ambient light sensor package that includes an ambient light sensor die having opposing first and second surfaces, a light sensor on the first surface of the ambient light sensor die, one or more conductive bumps on the second surface of the ambient light sensor die, and a light shielding layer on at least the first surface and the second surface of the ambient light sensor die. The light shielding layer defines an opening over the light sensor. The ambient light sensor package may further include a transparent cover between the first surface of the ambient light sensor die and the light shielding layer, and an adhesive that secures the transparent cover to the ambient light sensor die.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 27, 2019
    Inventors: Laurent HERARD, David GANI
  • Publication number: 20190154801
    Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.
    Type: Application
    Filed: November 20, 2017
    Publication date: May 23, 2019
    Inventor: David GANI
  • Publication number: 20190096788
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Patent number: 10147834
    Abstract: An electronic device includes a substrate, an optical sensor coupled to the substrate, and an optical emitter coupled to the substrate. A lens is aligned with the optical emitter and includes an upper surface and an encapsulation bleed stop groove around the upper surface. An encapsulation material is coupled to the substrate and includes first and second encapsulation openings therethrough aligned with the optical sensor and the lens, respectively.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: December 4, 2018
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Laurent Herard, David Gani
  • Patent number: 9793427
    Abstract: One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an optical sensor that includes a substrate and a sensor die. A through-hole extends through the substrate, and a trench is formed in a first surface of the substrate and is in fluid communication with the through-hole. The sensor die is attached to the first surface of the substrate and covers the first through-hole and a first portion of the trench. A second portion of the trench is left uncovered by the sensor die.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 17, 2017
    Assignee: STMICROELECTRONICS PTE LTD
    Inventor: David Gani