Patents by Inventor David H. Wells

David H. Wells has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167087
    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Inventors: Darwin A. Clampitt, David H. Wells, John D. Hopkins, Kevin Y. Titus
  • Patent number: 11011538
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 18, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Luan C. Tran, Jie Li, Anish A. Khandekar, Kunal Shrotri
  • Patent number: 10998222
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: May 4, 2021
    Assignee: Micron Technology, Inc.
    Inventor: David H Wells
  • Patent number: 10991759
    Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Sanh D. Tang, David H. Wells
  • Patent number: 10971360
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: April 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Anish A. Khandekar, Kunal Shrotri, Jie Li
  • Patent number: 10923494
    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Darwin A. Clampitt, David H. Wells, John D. Hopkins, Kevin Y. Titus
  • Publication number: 20210043834
    Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.
    Type: Application
    Filed: October 23, 2020
    Publication date: February 11, 2021
    Inventor: David H. Wells
  • Patent number: 10840443
    Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10770141
    Abstract: Memory devices provide a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also provided.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: September 8, 2020
    Assignee: Ovonyx Memory Technology, LLC
    Inventors: David H. Wells, Jun Liu
  • Patent number: 10727109
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: July 28, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Publication number: 20200161325
    Abstract: A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings.
    Type: Application
    Filed: November 19, 2018
    Publication date: May 21, 2020
    Inventors: Darwin A. Clampitt, David H. Wells, John D. Hopkins, Kevin Y. Titus
  • Publication number: 20200161168
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: January 23, 2020
    Publication date: May 21, 2020
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10608048
    Abstract: The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Christopher D. Cardon, Caner Onal
  • Patent number: 10580687
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10559466
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Anish A. Khandekar, Kunal Shrotri, Jie Li
  • Publication number: 20200020529
    Abstract: A transistor comprises channel material having first and second opposing sides. A gate is on the first side of the channel material and a gate insulator is between the gate and the channel material. A first insulating material has first and second opposing sides, with the first side being adjacent the second side of the channel material. A second insulating material of different composition from that of the first insulating material is adjacent the second side of the first insulating material. The second insulating material has at least one of (a), (b), and (c), where, (a): lower oxygen diffusivity than the first material, (b): net positive charge, and (c): at least two times greater shear strength than the first material. In some embodiments, an array of elevationally-extending strings of memory cells comprises such transistors. Other embodiments, including method, are disclosed.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Applicant: Micron Technology, Inc.
    Inventors: David H. Wells, Anish A. Khandekar, Kunal Shrotri, Jie Li
  • Patent number: 10504773
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: August 27, 2017
    Date of Patent: December 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Publication number: 20190371649
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • Publication number: 20190371648
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Applicant: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10438839
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: August 27, 2017
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells