Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first input of a multiplexer of a transmitter operably coupled to a data link; transmitting, by a digital data signal output of the multiplexer, the digital data signal to a receiver that is operably coupled to the data link; receiving, by a selection signal input of the multiplexer, a first selection signal that indicates an idle mode for the transmitter; receiving, by a second input of the multiplexer, a patterned data signal; and transmitting, by the digital data signal output and in response to the first selection signal, the patterned data signal to the receiver.

Abstract: Method and apparatus for transferring a data signal including receiving a digital data signal by a first data input of a transmitter multiplexer; inverting the digital data signal by a first inverter, thereby providing an inverted digital data signal; receiving the inverted digital data signal by a first inverted data input of the transmitter multiplexer; counting, by a first counter, a clock signal; transmitting, by the first counter and in response to the first counter counting a threshold number of clock cycles, a first selection signal to a first selection signal input of the transmitter multiplexer; and alternately transmitting, in response to the first selection signal and by a first digital data signal output of the transmitter multiplexer, the digital data signal and the inverted digital data signal as the transmitter output signal to a receiver, the receiver and the digital data signal output operably coupled to a data link.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A symmetric multiprocessor includes with a hierarchical ring-based interconnection network is disclosed. The symmetric processor includes a plurality of buses comprised on the symmetric multiprocessor, wherein each of the buses are configured in a circular topology. The symmetric multiprocessor also includes a plurality of multi-processing nodes interconnected by the buses to make a hierarchical ring-based interconnection network for conveying commands between the multi-processing nodes. The interconnection network includes a command network configured to transport commands based on command tokens, wherein the tokens dictate a destination of the command, a partial response network configured to transport partial responses generated by the multi-processing nodes, and a combined response network configured to combine the partial responses generated by the multi-processing nodes using combined response tokens.

Abstract: A time of day (TOD) synchronizer in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: A data processing system includes first and second processing nodes and response logic coupled by an interconnect fabric. A first coherence participant in the first processing node is configured to issue a memory access request specifying a target memory block, and a second coherence participant in the second processing node is configured to issue a probe request regarding a memory region tracked in a memory coherence directory. The first coherence participant is configured to, responsive to receiving the probe request after the memory access request and before receiving a systemwide coherence response for the memory access request, detect an address collision between the probe request and the memory access request and, responsive thereto, transmit a speculative coherence response. The response logic is configured to, responsive to the speculative coherence response, provide a systemwide coherence response for the probe request that prevents the probe request from succeeding.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled by a communication link includes receiving a first command from a first processing node. A link stall of the communication link is detected by a first link layer of the first processing node. A stop command is received at a first transaction layer of the first processing node from the first link layer. The first command is truncated by the first transaction layer into a first truncated command responsive to receiving the stop command. A command arbiter is instructed to stop issuing new commands. The first truncated command is forwarded to an asynchronous crossing buffer of the first processing node.

Abstract: Data processing in a data processing system including a plurality of processing nodes coupled to an interconnect includes receiving, by a fabric controller, a first command from a remote processing node via the interconnect. The fabric controller determines that the command includes a replay indication, the replay indication indicative of a replay event at one or more processing nodes of the plurality of processing nodes. The first command is dropped from a deskew buffer of the fabric controller responsive to the determining that the command includes the replay indication.

Abstract: A data processing system includes first and second processing nodes and response logic coupled by an interconnect fabric. A first coherence participant in the first processing node is configured to issue a memory access request specifying a target memory block, and a second coherence participant in the second processing node is configured to issue a probe request regarding a memory region tracked in a memory coherence directory. The first coherence participant is configured to, responsive to receiving the probe request after the memory access request and before receiving a systemwide coherence response for the memory access request, detect an address collision between the probe request and the memory access request and, responsive thereto, transmit a speculative coherence response. The response logic is configured to, responsive to the speculative coherence response, provide a systemwide coherence response for the probe request that prevents the probe request from succeeding.

Abstract: A time of day (TOD) synchronization mechanism in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: A time of day (TOD) synchronizer in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: A serial communication system includes a transmitting circuit for serially transmitting data via a serial communication link including N channels where N is an integer greater than 1. The transmitting circuit includes an input buffer having storage for input data frames each including M bytes forming N segments of M/N contiguous bytes. The transmitting circuit additionally includes a reordering circuit coupled to the input buffer. The reordering circuit includes a reorder buffer including multiple entries. The reordering circuit buffers, in each of multiple entries of the reorder buffer, a byte in a common byte position in each of the N segments of an input data frame. The reordering circuit sequentially outputs the contents of the entries of the reorder buffer via the N channels of the serial communication link.

Abstract: In a serial communication interface with transceivers that run on different clocks, an ACK transmit FIFO is used to track packets transmitted, and an ACK receive queue is used to track ACK bits for received packets. The ACK receive queue contains a number of entries, and training for the transceivers begins transmitting ACK bits from the ACK receive queue once the ACK receive queue has multiple valid ACK bits. When the ACK receive queue is less than a lower threshold, an ACK compensation mechanism sends one or more packets that make the ACK receive queue grow. When the ACK receive queue is more than an upper threshold, the ACK compensation mechanism sends one or more packets that make the ACK receive queue shrink. The combination of the ACK receive queue and the ACK compensation mechanism allow dynamically compensating for the different clocks of the two transceivers.