Patents by Inventor David J. Pignatelli
David J. Pignatelli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11256564Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.Type: GrantFiled: September 9, 2019Date of Patent: February 22, 2022Assignee: SK hynix Inc.Inventors: David J Pignatelli, Fan Zhang, Yu Cai
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Publication number: 20200004626Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.Type: ApplicationFiled: September 9, 2019Publication date: January 2, 2020Inventors: David J PIGNATELLI, Fan ZHANG, Yu CAI
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Patent number: 10409672Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.Type: GrantFiled: November 16, 2016Date of Patent: September 10, 2019Assignee: SK hynix Inc.Inventors: David J Pignatelli, Fan Zhang, Yu Cai
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Patent number: 10216625Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.Type: GrantFiled: March 14, 2013Date of Patent: February 26, 2019Assignee: SK Hynix Memory Solutions Inc.Inventor: David J. Pignatelli
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Patent number: 10148293Abstract: Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a log-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.Type: GrantFiled: March 16, 2016Date of Patent: December 4, 2018Assignee: SK Hynix Inc.Inventors: Fan Zhang, David J. Pignatelli, June Lee
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Publication number: 20180137003Abstract: A memory system and operating method thereof includes a semiconductor memory device, and a memory controller controlling actions of the memory device. The memory controller contains a processor executing instruction and programs stored in the memory controller, a memory characterizer characterizing the memory system, and generating an index decision table, an in-flight assessor assessing read command, and predicting a proposed error recovery action in accordance with the index decision table, and a selective decoder executing the proposed error recovery action.Type: ApplicationFiled: November 16, 2016Publication date: May 17, 2018Inventors: David J. Pignatelli, Fan Zhang, Yu Cai
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Patent number: 9953722Abstract: A method of controller optimization utilizing over-sampling read (OSR) in a memory device includes performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller, performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value, and determining whether a cell level falls in the range and transferring the second internal read measurement to the controller.Type: GrantFiled: January 8, 2016Date of Patent: April 24, 2018Assignee: SK Hynix Inc.Inventors: David J. Pignatelli, June Lee, Fan Zhang
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Patent number: 9733861Abstract: Memory systems may include a logical block address (LBA) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an LBA in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the LBA space was divided.Type: GrantFiled: July 25, 2016Date of Patent: August 15, 2017Assignee: SK hynix memory solutions Inc.Inventors: Fan Zhang, June Lee, David J. Pignatelli, Yu Cai
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Publication number: 20170024163Abstract: Memory systems may include a logical block address (LBA) space divided into a number of zones, a counter associated with each zone, each counter suitable for incrementing a count value when a read is performed on an LBA in the zone with which the counter is associated, and a controller suitable for calculating a temperature of each zone based on the count values of the counters, sorting the zones according to the calculated temperature, combining the zones into a number of superzones based on the sorting, and splitting the number of superzones into the number of zones into which the LBA space was divided.Type: ApplicationFiled: July 25, 2016Publication date: January 26, 2017Inventors: Fan ZHANG, June LEE, David J. PIGNATELLI, Yu CAI
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Patent number: 9507705Abstract: A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations.Type: GrantFiled: September 19, 2013Date of Patent: November 29, 2016Assignee: SK hynix memory solutions Inc.Inventor: David J. Pignatelli
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Patent number: 9502127Abstract: Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number of hard reads, and estimating a conditional probability density of a cell voltage based on the hard reads and the background reads.Type: GrantFiled: March 17, 2016Date of Patent: November 22, 2016Assignee: SK hynix memory solutions Inc.Inventors: Fan Zhang, David J. Pignatelli, June Lee
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Publication number: 20160276036Abstract: Methods of determining distributions may include performing a number of hard reads, performing a number of background reads at a frequency based on the number of hard reads, and estimating a conditional probability density of a cell voltage based on the hard reads and the background reads.Type: ApplicationFiled: March 17, 2016Publication date: September 22, 2016Inventors: Fan ZHANG, David J. PIGNATELLI, June LEE
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Publication number: 20160277041Abstract: Methods for decoding information stored on a memory may include performing a hard read at an initial threshold and determining a first distribution percentage, performing a hard read at a subsequent threshold and determining a second distribution percentage, generating a least-likelihood ratio (LLR) based on the hard reads performed at the initial and subsequent thresholds, and based on the first and second distribution percentages, and soft decoding the information based on the generated LLR.Type: ApplicationFiled: March 16, 2016Publication date: September 22, 2016Inventors: Fan ZHANG, David J. PIGNATELLI, June LEE
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Publication number: 20160202934Abstract: A method of controller optimization utilizing over-sampling read (OSR) in a memory device includes performing a first internal read at a predetermined threshold level and transferring the first internal read measurement to the controller, performing a second internal read in a range that is between the predetermined threshold level plus a first predetermined value and the predetermined threshold level minus a second predetermined value, and determining whether a cell level falls in the range and transferring the second internal read measurement to the controller.Type: ApplicationFiled: January 8, 2016Publication date: July 14, 2016Inventors: David J. Pignatelli, June Lee, Fan Zhang
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Publication number: 20160179401Abstract: A system includes a memory device including a plurality of blocks and a controller suitable for controlling the memory device. The controller creates a k-dimensional array from the plurality of the blocks, where k is greater than 2, and selects best candidate blocks from the k-dimensional array with respect to the k metrics. The k-dimensional array includes 2-dimensional linked list arrays.Type: ApplicationFiled: December 9, 2015Publication date: June 23, 2016Inventors: Fan ZHANG, David J. PIGNATELLI, Yu Chin Fabian LIM
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Patent number: 9348758Abstract: A method of relating the user logical block address (LBA) of a page of user data to the physical block address (PBA) where the data is stored in a RAID architecture reduces to size of the tables by constraining the location to which data of a plurality of LBAs may be written. Chunks of data from a plurality of LBAs may be stored in a common page of memory and the common memory pages is described by a virtual block address (VBA) referencing the PBA, and each of the LBAs uses the same VBA to read the data.Type: GrantFiled: March 15, 2013Date of Patent: May 24, 2016Assignee: SK Hynix memory solutions inc.Inventor: David J. Pignatelli
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Publication number: 20140089630Abstract: A method of relating the user logical block address (LBA) of a page of user data to the physical block address (PBA) where the data is stored in a RAIDed architecture reduces to size of the tables by constraining the location to which data of a plurality of LBAs may be written. Chunks of data from a plurality of LBAs may be stored in a common page of memory and the common memory pages is described by a virtual block address (VBA) referencing the PBA, and each of the LBAs uses the same VBA to read the data.Type: ApplicationFiled: March 15, 2013Publication date: March 27, 2014Inventor: David J. Pignatelli
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Publication number: 20140089567Abstract: A flash memory management method and apparatus provides for the separation of the command and data paths so that communication paths may be used more efficiently, taking account of the characteristics of NAND FLASH circuits where the times to read, write and erase data differ substantially. A unique sequence identifier is assigned to a write command and associated data and association of the data and commands are validated prior to writing to the memory by comparing the unique sequence numbers of the data and command prior to executing the command. This comparison is performed after the data and command have traversed the communication paths.Type: ApplicationFiled: March 14, 2013Publication date: March 27, 2014Applicant: Violin Memory IncInventor: David J. Pignatelli
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Publication number: 20140089569Abstract: A method of managing a non-volatile memory system is described where data elements stored in a buffer are characterized by attributes and a write data tag is created for the data elements. A plurality of write data tag queues is maintained so that different data attributes may be applied as sorting criteria when the data elements are formed into pages for storage in the non-volatile memory. The memory system may be organized as a RAID system and a write data tag queue may be associated with a specific RAID group such that the data pages may be written from a buffer to the non-volatile memory in accordance with the results of sorting each write data queue. The data elements stored in the buffer may be received from a user, or be read from the non-volatile memory during the performance of system overhead operations.Type: ApplicationFiled: September 19, 2013Publication date: March 27, 2014Inventor: David J. Pignatelli
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Publication number: 20130318285Abstract: An apparatus and method of managing the operation of a plurality of FLASH chips provides for a physical layer (PHY) interface to a FLASH memory circuit having a plurality of FLASH chips having a common interface bus. The apparatus has a PHY for controlling the voltages on the interface pins in accordance with a microprogrammable state machine. A data transfer in progress over the bus may be interrupted to perform another command to another chip on the shared bus and the data transfer may be resumed after completion of the another command.Type: ApplicationFiled: March 15, 2013Publication date: November 28, 2013Applicant: VIOLIN MEMORY INCInventor: David J. Pignatelli