Patents by Inventor David J. Sager

David J. Sager has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10725755
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffrey J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Publication number: 20180060049
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: June 6, 2017
    Publication date: March 1, 2018
    Inventors: DAVID J. SAGER, RUCHIRA SASANKA, RON GABOR, SHLOMO RAIKIN, JOSEPH NUZMAN, LEEOR PELED, JASON A. DOMER, HO-SEOP KIM, YOUFENG WU, KOICHI YAMADA, TIN-FOOK NGAI, HOWARD H. CHEN, JAYARAM BOBBA, JEFFREY J. COOK, OMAR M. SHAIKH, SURESH SRINIVAS
  • Patent number: 9880842
    Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
  • Patent number: 9672019
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Grant
    Filed: December 25, 2010
    Date of Patent: June 6, 2017
    Assignee: Intel Corporation
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Patent number: 9189233
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. For example, a method according to one embodiment comprises: analyzing a single-threaded region of executing program code, the analysis including identifying dependencies within the single-threaded region; determining portions of the single-threaded region of executing program code which may be executed in parallel based on the analysis; assigning the portions to two or more parallel execution tracks; and executing the portions in parallel across the assigned execution tracks.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: November 17, 2015
    Assignee: INTEL CORPORATION
    Inventors: Ruchira Sasanka, Abhinav Das, Jeffrey J. Cook, Jayaram Bobba, Arvind Krishnaswamy, David J. Sager, Suresh Srinivas
  • Patent number: 8914617
    Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
    Type: Grant
    Filed: December 24, 2010
    Date of Patent: December 16, 2014
    Assignee: Intel Corporation
    Inventors: Shlomo Raikin, David J. Sager, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman, Adi Yoaz, Omer Golz
  • Patent number: 8850165
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: September 30, 2014
    Assignee: Intel Corporation
    Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
  • Publication number: 20140281424
    Abstract: A mechanism for tracking the control flow of instructions in an application and performing one or more optimizations of a processing device, based on the control flow of the instructions in the application, is disclosed. Control flow data is generated to indicate the control flow of blocks of instructions in the application. The control flow data may include annotations that indicate whether optimizations may be performed for different blocks of instructions. The control flow data may also be used to track the execution of the instructions to determine whether an instruction in a block of instructions is assigned to a thread, a process, and/or an execution core of a processor, and to determine whether errors have occurred during the execution of the instructions.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Jayaram Bobba, Ruchira Sasanka, Jeffrey J. Cook, Abhinav Das, Arvind Krishnaswamy, David J. Sager, Jason M. Agron
  • Patent number: 8347066
    Abstract: Replay instruction morphing. One disclosed apparatus includes an execution unit to execute an instruction. A replay system replays an altered instruction if the execution unit executes the instruction erroneously.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Douglas M. Carmean, David J. Sager, Thomas F. Toll, Karol F. Menezes
  • Publication number: 20120042151
    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
    Type: Application
    Filed: September 10, 2010
    Publication date: February 16, 2012
    Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton
  • Publication number: 20110239221
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
  • Publication number: 20110208918
    Abstract: Methods and apparatus relating to a hardware move elimination and/or next page prefetching are described. In some embodiments, a logic may provide hardware move eliminations based on stored data. In an embodiment, a next page prefetcher is disclosed. Other embodiments are also described and claimed.
    Type: Application
    Filed: December 24, 2010
    Publication date: August 25, 2011
    Inventors: Shlomo Raikin, David J. Sager, Zeev Sperber, Evgeni Krimer, Ori Lempel, Stanislav Shwartsman, Adi Yoaz, Omer Golz
  • Patent number: 7987346
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: David Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
  • Publication number: 20110167416
    Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
    Type: Application
    Filed: December 25, 2010
    Publication date: July 7, 2011
    Inventors: David J. Sager, Ruchira Sasanka, Ron Gabor, Shlomo Raikin, Joseph Nuzman, Leeor Peled, Jason A. Domer, Ho-Seop Kim, Youfeng Wu, Koichi Yamada, Tin-Fook Ngai, Howard H. Chen, Jayaram Bobba, Jeffery J. Cook, Omar M. Shaikh, Suresh Srinivas
  • Publication number: 20110113222
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Application
    Filed: January 21, 2011
    Publication date: May 12, 2011
    Applicant: INTEL CORPORATION
    Inventors: David W. BURNS, James D. ALLEN, Michael D. UPTON, Darrell D. BOGGS, David J. SAGER
  • Patent number: 7877583
    Abstract: In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting counters are associated with each thread that serve as a multiplier for the value to be used in the thread precedence counter. The value in the starting counters are manipulated so as to prevent one thread from getting undue priority to the resources of the multi-threaded processor.
    Type: Grant
    Filed: November 7, 2008
    Date of Patent: January 25, 2011
    Assignee: Intel Corporation
    Inventors: David W. Burns, James D. Allen, Michael D. Upton, Darrell D. Boggs, David J. Sager
  • Patent number: 7863764
    Abstract: A torque converter-mounted generator is provided that, along with power electronics, offers at least two types of electrical power output and may be attached to a transmission without impacting the axial length of a powertrain in comparison to a powertrain with an identical transmission and a torque converter not having a generator mounted thereto. Different torque-converter mounted generators and power electronics configurations providing different combinations of electrical power voltages may be offered for use with a given transmission type, thus allowing flexibility in meeting customer needs without unduly impacting assembly of the powertrains. A method of assembling transmissions is also provided.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: January 4, 2011
    Assignee: GM Global Technology Operations, Inc.
    Inventors: Robert Franklin Combs, David J. Sagers, Leroy K. Johnson
  • Publication number: 20090327661
    Abstract: Methods and apparatus relating to mechanisms to handle free physical register identifiers for SMT (Simultaneous Multi-Threading) out-of-order processors are described. In some embodiments, a physical register file stores both speculative data and architectural data corresponding to a plurality of registers. A free list logic may maintain free physical register identifiers corresponding to the plurality of registers. An instruction may read the architectural data from the physical register file at dispatch. Other embodiments are also described and claimed.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventors: Zeev Sperber, David J. Sager, Fernando Latorre, Ori Lempel, Evgeni Krimer, Bishara Shomar
  • Patent number: RE44494
    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton
  • Patent number: RE45487
    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton