Patents by Inventor David J. Seymour
David J. Seymour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6977196Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.Type: GrantFiled: August 18, 2003Date of Patent: December 20, 2005Assignee: Texas Instruments IncorporatedInventors: Darius L. Crenshaw, Stuart M. Jacobsen, David J. Seymour
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Patent number: 6967531Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an intermediate signal in response to an input signal. The second circuit may be configured to generate a plurality of output signals in response to the intermediate signal. Each of the output signals may be (i) an amplified versions of the input signal and (ii) isolated between each of the other output signals.Type: GrantFiled: February 28, 2003Date of Patent: November 22, 2005Assignee: Sirenza Microdevices, Inc.Inventor: David J. Seymour
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Patent number: 6698082Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.Type: GrantFiled: August 28, 2001Date of Patent: March 2, 2004Assignee: Texas Instruments IncorporatedInventors: Darius L. Crenshaw, Stuart M. Jacobsen, David J. Seymour
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Publication number: 20030042560Abstract: The present invention provides a method and product-by-method of integrating a bias resistor in circuit with a bottom electrode of a micro-electromechanical switch on a silicon substrate. The resistor and bottom electrode are formed simultaneously by first sequentially depositing a layer of a resistor material (320), a hard mask material (330) and a metal material (340) on a silicon substrate forming a stack. The bottom electrode and resistor lengths are subsequently patterned and etched (350) followed by a second etching (360) process to remove the hard mask and metal materials from the defined resistor length. Finally, in a preferred embodiment, the bottom electrode and resistor structure is encapsulated with a layer of dielectric which is patterned and etched (370) to correspond to the defined bottom electrode and resistor.Type: ApplicationFiled: August 28, 2001Publication date: March 6, 2003Inventors: Darius L. Crenshaw, Stuart M. Jacobsen, David J. Seymour
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Patent number: 6529080Abstract: An apparatus comprising an amplifier and a circuit. The amplifier may be configured to amplify an input signal. The circuit may be configured to (i) control the amplifier, (ii) compensate for non-linear characteristics of the amplifier, (iii) increase third-order intercept (TOI) and (iv) increase the output 1 dB compression point (P1 dB).Type: GrantFiled: September 11, 2001Date of Patent: March 4, 2003Assignee: Sirenza Microdevices, Inc.Inventors: David J. Seymour, Randy L. Cochran, Timothy M. Gittemeier
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Patent number: 5459343Abstract: A semiconductor device which includes a channel region of predetermined conductivity type having a pair of opposing surfaces (11 or 33) , a control element of opposite conductivity type disposed on one of the opposing surfaces (13 or 31) and a pair of spaced apart electrodes (17, 19 or 35, 37) disposed over the other of the opposing surfaces. The control element and channel region form a pn junction therebetween. An electrically insulating layer (15) can be disposed between the spaced apart electrodes (17, 19) and the channel region (11) in a high frequency embodiment.Type: GrantFiled: March 4, 1994Date of Patent: October 17, 1995Assignee: Texas Instruments IncorporatedInventors: David J. Seymour, Frank J. Morris
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Patent number: 5047829Abstract: Monolithic gallium arsenide limiters (30) formed of p-i-n diodes (32, 34) that are distributed devices between conductors of coplanar waveguide sections (40, 42, 44) are disclosed. The diode doped regions underlie the coplanar conductors and the diode intrinsic region underlies the coplanar waveguide gap. The grounded coplanar segments connect to a backside ground through vias (74).Type: GrantFiled: October 30, 1986Date of Patent: September 10, 1991Assignee: Texas Instruments IncorporatedInventors: David J. Seymour, David D. Heston, Randall E. Lehmann
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Patent number: 4810980Abstract: This invention provides a switched limiter with variable attenuation designed with monolithic GaAs p-i-n diodes. Greater than 30 dB of small-signal variable attenuation is achieved at X band frequencies, with a minimum insertion loss of 0.5 dB. The variable attenuation switched limiter provides 15 dB of isolation to a +30 dBm input signal. Under bias conditions that result in variable attenuation the variable attenuation switched limiter input impedance remains matched. When used as a passive limiter, 7 dB of limiting has been achieved for a +30 dBm input signal at 10 GHz.Type: GrantFiled: June 4, 1987Date of Patent: March 7, 1989Assignee: Texas Instruments, Inc.Inventors: David D. Heston, David J. Seymour, Randall E. Lehmann
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Patent number: 4658220Abstract: A monolithic low noise variable gain amplifier with series feedback includes a dual gate field effect transistor (DGFET) having a common source FET and a common gate FET with scaled gate widths and/or an interelectrode matching element connected to ground through a capacitor positioned between the two gates for reducing the minimum noise figure of the common gate FET and establishing the output load for the common source FET, and an inductive series feedback line for connecting the common source FET to ground. The amount of series feedback between the source and ground of the DGFET as well as the appropriate output load obtained through gate width scaling are selected to make the conjugate input impedance equal to the optimum impedance for a simultaneous noise match and power match.Type: GrantFiled: September 6, 1985Date of Patent: April 14, 1987Assignee: Texas Instruments IncorporatedInventors: David D. Heston, Randall E. Lehmann, David J. Seymour
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Patent number: 4525678Abstract: A monolithic amplifier having a common-gate input stage with a device transconductance which is higher than required for input match, and a load impedance presented to the common-gate stage which is not conjugate matched. The present invention teaches a common-gate configuration using an FET with higher transconductance and a higher output load impedance. Over narrower bandwidths, excellent input match is thus obtained with noise figures at least as good as those obtained with the common-source approach. This combination of noise figure and input match is achieved in a compact monolithic structure.Type: GrantFiled: July 6, 1982Date of Patent: June 25, 1985Assignee: Texas Instruments IncorporatedInventors: Randall E. Lehmann, Gailon E. Brehm, David J. Seymour
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Patent number: 4361105Abstract: An improvement in a barge-carrying flotation-loaded waterborne vessel. A hollow interior defines upper and lower longitudinal barge holds arranged in vertical rows of aligned tiers, each hold being flooded during the time it is loaded and unloaded. There is at least one loading lock at one end of the vessel for enabling flotation loading of each vertical row of barge holds; each lock has a pair of side bulkheads and a bottom, and gate means for separating the lock from and opening it to the outside for flotation loading and unloading of one barge at a time. There is also a separate lock gate for each tier of each row for connecting a hold of each row to a lock. In each lock there are sets of barge support panels, each pivotally attached by a horizontal longitudinally extending pivot to one of the side bulkheads, at least one set being disposed on each side of the lock adjacent to and approximately on a level with each upper longitudinal barge hold.Type: GrantFiled: December 8, 1980Date of Patent: November 30, 1982Assignee: Wharton Shipping CorporationInventors: William E. Kirby, David J. Seymour
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Patent number: 4305342Abstract: A barge-carrying vessel of the flotation loading and unloading type. Each barge-stowage hold has parallel, vertical side walls that are only slightly further apart from each other than the width of the barges to be stowed. The barges are held down against the bottom of the hold, enabling transfer of buoyancy from the barges to the vessel when the hold is flooded. For this purpose, a series of guides is secured to one side wall of the hold, each guide comprising a pair of parallel vertical tracks. In between each pair of tracks is a wedge having a sloping outer face for engagement with a barge in a wedging manner to force this barge against the opposite side wall. The wedges are raised and lowered as needed, and are positively secured in place in their barge-hold down position.Type: GrantFiled: December 31, 1979Date of Patent: December 15, 1981Assignee: Wharton Shipping CorporationInventors: William E. Kirby, David J. Seymour
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Patent number: 4147123Abstract: A transportation method and a barge-carrying waterborne vessel in which there is flotation loading and unloading, with the loading being assisted by water flow from the gate into the flooded vessel and toward the opposite end of the vessel from the gate. For unloading, the water flows in the opposite direction, toward the gate. Preferably, loading is through a gate in the stern while water is being pumped out from a sump at the forward end of a hold. When barges are fully loaded into the hold, the stern gate is closed and the hold may be dried out; then the barges are secured in place against movement relative to the vessel. There may be more than one hold having at least one longitudinal bulkhead dividing the holds. There may be either a separate gate for each hold or a transfer system in which each longitudinal bulkhead has an archway providing a passageway joining adjacent holds. During lateral transfer water jets may play against the sides of the barge to cause lateral movement.Type: GrantFiled: October 14, 1977Date of Patent: April 3, 1979Assignee: Wharton Shipping CorporationInventors: William E. Kirby, David J. Seymour
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Patent number: 4135468Abstract: A transportation method and barge-carrying water-borne vessel therefor having a hull with rigid supporting and hull-reinforcing structure, a bow, a stern, and side walls providing a series of buoyancy compartments. The hull has a hollow interior defining at least one hold extending most of the length of said vessel. The bottom of the hold is always below the level of the sea. Water can be placed from the sea into the hold and can be pumped out from it. A gate at one end of the vessel is opened for flotation loading of the hold, when the hold is partially flooded, with buoyant cargo carriers such as barges, lighters and pontoons. Each such carrier may be held down against the bottom of the hold. A collision bulkhead located adjacent the gate enables closing the hold off in a watertight manner, and this collision bulkhead can be opened to enable the flotation loading and unloading.Type: GrantFiled: March 9, 1977Date of Patent: January 23, 1979Assignee: Wharton Shipping CorporationInventors: William E. Kirby, David J. Seymour
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Patent number: 3938274Abstract: A purse-seine net, lures, or other fish catching devices are used in conjunction with a fishing vessel having a normally closed opening through the side of its hull below waterline. When the purse-seine net is used, a looped opening at the end of the net is placed over and around the opening through the vessel's hull, and the fish are transferred from the net in through the hull, as by suction, into a hold area where they are separated from the sea water; then the sea water is returned to the sea. Trim and stability problems of the vessel are solved by a novel system incorporating one or more compensating tanks, a ballast pump, and novel hull design.Type: GrantFiled: March 3, 1975Date of Patent: February 17, 1976Assignee: Anthony M. UrsichInventor: David J. Seymour
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Patent number: 3934530Abstract: A vessel for transporting floatably onloaded and offloaded cargo (typically barges) is disclosed. A hull having a well deck surrounded on three sides by the bow, port and starboard vessel's sides has a plurality of ballast tanks adapted to be filled with sea water. When the ballast tanks are flooded, the hull is in a loading configuration wherein the well deck is submerged so that cargo can be floated over the well deck and positioned thereon. At this submerged position of the well deck, the continuous sidewalls of the vessel are interrupted by a series of horizontally elongate water level ports constituting a large interruption of the water plane of the vessel. These ports are concentrated in the area of the forward well deck bulkhead and impede the formation of standing waves within the vessel whereby destructive motion between the carrier vessel and the floating cargo can be prevented from damaging the carrier vessel, floating cargo, or both.Type: GrantFiled: October 17, 1974Date of Patent: January 27, 1976Assignee: Inter-HullInventors: Miklos M. Kossa, David J. Seymour
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Patent number: RE30040Abstract: A vessel for transporting, on a body of water, cargo consisting of barges, pontoons, and lighters, and other floating cargoes. The hull has a bow, a stern, and water-tight buoyancy compartments in side walls. The hull also has a perforate bottom shell with rigid supporting and reinforcing structure, enabling the cargo hold to be flooded and open to the sea under all conditions while loading, in transit, and during discharge. A hinged gate is provided at either or both ends of the hull for rapid flotation loading and unloading of the floating cargo, and each gate closed during transportation of the cargo. The vessel carries means for moving the cargo into, out of, and within the hold. A series of vertical pistons secure the floating cargo units by exerting a downward force to bring the cargo to bear on the hull structure. The water in the hold, having communication with the sea, provides buoyancy for the cargoes secured therein.Type: GrantFiled: September 27, 1977Date of Patent: July 3, 1979Assignee: Wharton Shipping CorporationInventors: William E. Kirby, David J. Seymour