Patents by Inventor David K. Hwang

David K. Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220310831
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: June 14, 2022
    Publication date: September 29, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Patent number: 11393920
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220102539
    Abstract: Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: September 28, 2020
    Publication date: March 31, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, John F. Kaeding, Richard J. Hill, Scott E. Sills
  • Publication number: 20220069133
    Abstract: Some embodiments include an integrated assembly having an upwardly-extending structure with a sidewall surface. Two-dimensional-material extends along the sidewall surface. First electrostatic-doping-material is adjacent a lower region of the two-dimensional-material, insulative material is adjacent a central region of the two-dimensional-material, and second electrostatic-doping-material is adjacent an upper region of the two-dimensional-material. A conductive-gate-structure is over the first electrostatic-doping-material and adjacent to the insulative material. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, Richard J. Hill, Gurtej S. Sandhu
  • Publication number: 20220068932
    Abstract: Some embodiments include an integrated assembly having first conductive structures extending along a first direction. Spaced-apart upwardly-opening container-shapes are over the first conductive structures. Each of the container-shapes has a first sidewall region, a second sidewall region, and a bottom region extending from the first sidewall region to the second sidewall region. Each of the first and second sidewall regions includes a lower source/drain region, an upper source/drain region, and a channel region between the upper and lower source/drain regions. The lower source/drain regions are electrically coupled with the first conductive structures. Second conductive structures extend along a second direction which crosses the first direction. The second conductive structures have gate regions operatively adjacent the channel regions. Storage elements are electrically coupled with the upper source/drain regions. Some embodiments include methods of forming integrated assemblies.
    Type: Application
    Filed: July 14, 2021
    Publication date: March 3, 2022
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, Richard J. Hill, Gurtej S. Sandhu
  • Patent number: 10643906
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Publication number: 20190189515
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Patent number: 8691656
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Patent number: 8211763
    Abstract: A method of forming a vertical field effect transistor includes etching an opening into semiconductor material. Sidewalls and radially outermost portions of the opening base are lined with masking material. A semiconductive material pillar is epitaxially grown to within the opening adjacent the masking material from the semiconductor material at the opening base. At least some of the masking material is removed from the opening. A gate dielectric is formed radially about the pillar. Conductive gate material is formed radially about the gate dielectric. An upper portion of the pillar is formed to comprise one source/drain region of the vertical transistor. Semiconductive material of the pillar received below the upper portion is formed to comprise a channel region of the vertical transistor. Semiconductor material adjacent the opening is formed to comprise another source/drain region of the vertical transistor. Other aspects and implementations are contemplated.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: July 3, 2012
    Assignee: Micron Technologies, Inc.
    Inventors: Larson D. Lindholm, David K. Hwang
  • Patent number: 8178911
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, Larson Lindholm
  • Publication number: 20120003810
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Application
    Filed: September 8, 2011
    Publication date: January 5, 2012
    Applicant: Micron Technology, Inc.
    Inventors: David K. Hwang, Larson Lindholm
  • Publication number: 20110318921
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Application
    Filed: September 7, 2011
    Publication date: December 29, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Patent number: 8030168
    Abstract: The invention includes methods of electrically interconnecting different elevation conductive structures, methods of forming capacitors, methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM, and methods of forming DRAM memory cells. In one implementation, a method of electrically interconnecting different elevation conductive structures includes forming a first conductive structure comprising a first electrically conductive surface at a first elevation of a substrate. A nanowhisker is grown from the first electrically conductive surface, and is provided to be electrically conductive. Electrically insulative material is provided about the nanowhisker. An electrically conductive material is deposited over the electrically insulative material in electrical contact with the nanowhisker at a second elevation which is elevationally outward of the first elevation, and the electrically conductive material is provided into a second conductive structure.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Brett W. Busch, David K. Hwang, F. Daniel Gealy
  • Patent number: 8022473
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 20, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, Larson Lindholm
  • Publication number: 20110133263
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Application
    Filed: February 16, 2011
    Publication date: June 9, 2011
    Applicant: Micron Technology, Inc.
    Inventors: DAVID K. HWANG, Larson Lindholm
  • Patent number: 7948030
    Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: May 24, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
  • Patent number: 7935999
    Abstract: A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: May 3, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Gordon A. Haller, David K. Hwang, Sanh Dang Tang, Ceredig Roberts
  • Patent number: 7897465
    Abstract: A semiconductor device fabricated in the semiconductor substrate includes a FinFET transistor having opposed source and drain pillars, and a fin interposed between the source and drain pillars. A cavity is formed in the semiconductor substrate extending at least partially between the fin and the semiconductor substrate. The cavity may be formed within a shallow trench isolation structure, and it may also extend at least partially between the semiconductor substrate and one or both of the pillars. The cavities increase the impedance between the semiconductor substrate and the fin and/or pillars to decrease the sub-threshold leakage of the FinFET transistor.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 1, 2011
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, Larson Lindholm
  • Publication number: 20100327369
    Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F3. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
    Type: Application
    Filed: September 3, 2010
    Publication date: December 30, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
  • Patent number: 7808041
    Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang