Abstract: A server with a flexible cooling scheme is disclosed. The server comprises a case and a fan. When the server is in a first cooling configuration the fan is configured to force the gas past a first area to be cooled and out to the outside of the case through a second opening in the case. When the server is in a second cooling configuration, the server further comprises a heat exchanger located in the first area and configured to seal the first opening in the case thereby preventing outside gas from entering the first area. When the server is in the second cooling configuration, a sealing device is configured to seal the second opening thereby redirecting the first fan to force the gas past the first area to be cooled and back into the first area, thereby re-circulating the gas inside the case.

Abstract: A server with a flexible cooling scheme is disclosed. The server comprises a case having an inside and an outside. A first fan is positioned inside the case and configured to draw gas from a first area inside the case and force the gas past a first area to be cooled. A first opening in the case is configured to allow gas from outside the case to enter the first area. When the server is in a first cooling configuration the first fan is configured to force the gas past the first area to be cooled and out to the outside of the case through a second opening in the case. When the server is in a second cooling configuration, the server further comprises a heat exchanger located in the first area and configured to seal the first opening in the case thereby preventing outside gas from entering the first area.

Abstract: A system for ventilating electronic equipment and suppressing the radiation of electromagnetic interference (EMI) from the electronic equipment. More particularly, the present invention relates to a ventilation port and EMI wave-guide. There is provided corrugated spring member is compressed between a first plate and a second plate so as to define a plurality of ducts, each having a depth and a cross-sectional width. The spring member is in electrical contact with the first plate and the second plate.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A semiconductor device assembly according to the present invention may comprise a semiconductor die having at least one contact pad thereon and a package substrate having at least one lead pad thereon. The package substrate is sized to receive the semiconductor die so that the contact pad on the semiconductor die is substantially aligned with the lead pad on the package substrate when the semiconductor die is positioned on the package substrate. A coil spring is positioned between the contact pad on the semiconductor die and the lead pad on the package substrate so that the axis of the coil spring is substantially parallel to the contact pad contained on the semiconductor die and the lead pad contained on the package substrate.

Abstract: A method and system of maintaining strong ordering in a multiprocessor computer system having a coherent memory. Memory transactions are send from one or more processors to a processor agent. The processor agent sends the transactions to a memory agent via a crossbar switch. The memory agent performs memory coherency operations and sends memory transactions back to the processor agents via the crossbar switch. The crossbar switch, however, may alter the order in which the memory transactions are forwarded to the processor agent. Therefore, the memory agent also sends a timestamp for each memory transaction directly to the processor agent via a dedicated link. An arbitrator within the processor agent receives the timestamps and the memory transactions. Using the timestamps, the arbitrator reorders the memory transactions and sends the transactions to the processors in the order in which the transactions were sent. In addition, the memory agent sends a parity signal with each timestamp.

Abstract: The multi-node multiprocessor system with globally shared memory is partitioned into groups of nodes called error containment clusters of nodes or ECCNs. The nodes would be partitioned such that an ECCN resides on a column of nodes or a row of nodes. Within each ECCN there is coherent memory sharing. Between the ECCNs, the communication is through a messaging protocol. The memory within each node is also partitioned into protected and unprotected memory. Unprotected memory is used for messaging and protected memory is used for sharing. A failure in an error containment cluster would corrupt the memory within that cluster, specifically the protected memory within that cluster and also the unprotected memory used by that cluster to communicate with the other clusters. However, the other clusters could continue to run because their protected memory would be unaffected, and could continue to communicate through the remaining unprotected memory.

Abstract: There is disclosed a shared multiprocessing system with several nodes, or processing units, interconnected together for communication purposes by a dual channeled crossbar switch. Several such multichannel crossbar switches can be linked together to form a large cohesive processing system where processing units from one node can access memory from another node on the same crossbar or from another node on a different crossbar. The interconnection between crossbars is accomplished by a circular ring. In operation, the system allows for long memory latencies while not increasing the length of short (local) memory latencies. This is accomplished by storing the bulk of long latency requests at the local processing unit and only sending the request when there is an actual availability of communication capacity to handle the long latency request.

Abstract: A processing system 100 is provided which includes first and second hypernodes 101, each of the hypernodes 101 having at least first and second coherent interfaces 106. At least first and second interconnect network 107 are provided, the first network 107 coupling the first interfaces 106 of the first and second hypernodes 101 and the second interconnect network 107 coupling the second interfaces 106 of the first and second hypernodes 101.

Abstract: A computer system having a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: A computer system comprises a plurality of independent processors which can either execute a separate process for each processor, or execute parallel process operations across multiple processors for one process. The computer system includes a set of communication registers divided into a group of frames and a set of semaphores which correspond respectively to the registers. Typical processes have both serial and parallel code segments. During serial execution, a process is executed by a single processor, but when a parallelization instruction is encountered, which indicates that code can be executed in parallel, a semaphore is posted to invite other processors to join in parallel execution of the process. If any other processors in the system are idle, those processors detect the semaphore and accept a thread of process operation. Two or more processors may join in parallel operation if sufficient operations are available.

Abstract: A vector processing computer (20) includes a memory control unit (22), main memory (99), a central processor (156), a service processing unit (42) and a plurality of input/output processors (54, 68). The central processor (156) includes a physical cache unit (100), an address translation unit (118), an instruction processing unit (126), an address scalar unit (142), a vector control unit (144), an odd pipe vector processing unit (148) and an even pipe vector processing unit (150). Vector elements are transmitted from memory, either main memory (99), a physical cache unit (100) or a logical cache (326) through a source bus (114) where the elements are alternately loaded into the vector processing units (148, 150). The resulting vectors are transmitted through a destination bus (114) to either the physical cache unit (100), the main memory (99), the logical cache (326) or to an input/output processor (54).

Abstract: A computer (20) is configured for optimizing the processing rate of instructions and the throughput of data. The computer (20) includes a main memory (99), a memory control unit (22), a physical cache unit (100), and a central processor (156). A instruction processing unit (126) is included within the central processor (156). The function of the instruction processing unit (126) is to decode instructions and produce instruction execution commands or directing the execution of the instructions within the central processor (156). Instructions are transferred from the main memory (99) into a register (180) where the address fields of the instructions are decoded to produce a cracked instruction and these instructions are stored in a logical instruction cache (210). As the cracked instructions are selected they are transferred to an output buffer and decoder (214) where the remaining fields of the instructions are decoded to produce instruction execution commands.

Abstract: A computer includes a memory for storing the machine instructions therein and an arithmetic logic unit for carrying out logical and arithmetic operations. An instruction processing unit is provided for receiving and decoding machine instructions which are received from the memory. The instruction processing unit produces an entry address for the first microinstruction which corresponds to the machine instruction which was decoded by the instruction processing unit. A dispatch control store is connected to receive the entry address and further has stored therein the first microinstruction for each of the machine instructions. The dispatch control store produces a selected one of the microinstructions stored therein upon receipt of the entry address. A main control store is provided for storing therein all of the microinstructions for each of the machine instructions other than the first microinstruction for each of the machine instructions.

Abstract: A diagnostic circuit is used to test the operation of a complex digital system by transferring operands to and from a plurality of registers (12, 14, 16). In a typical application the registers (12, 14, 16) in operation utilize parallel data transfers. For diagnostic purposes the registers (12, 14, 16) are connected serially and, in response to selected shift commands, data can be shifted either right or left through the registers (12, 14, 16). First and second buses (18, 20) provide serial, bidirectional paths for data transfer between the group of registers (12, 14, 16) and a service processing unit (26). In response to commands generated by the service processing unit (26) the registers (12, 14, 16) can be loaded right or left and read right or left. Whenever data is being read from the registers (12, 14, 16) the output data is recirculated back into the registers such that a complete cycle results in the original state being restored in the registers (12, 14, 16).

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of the storage elements to a plurality of data lines. Protection circuitry is provided that is connected to the address lines for storing flags corresponding to selected groups of the storage elements to be protected. Write circuitry is provided that is connected to the address lines and to the array of storage elements for preventing the writing into the storage elements addressed by the address lines when the address is within the address of the protected groups. Control circuitry is provided that is connected to the protect circuit and the write circuit for controlling the input of the protect group addresses and for enabling the write circuit means during a write operation. The memory apparatus further includes the capability to provide protection from writing from a direct memory access source or from a central processing unit source.

Abstract: A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor.

Abstract: A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.

Abstract: A memory apparatus including an array of storage elements connected to several addressing lines for selectively connecting a group of the storage elements to multiple data lines. The memory apparatus further includes a parity circuit connected to the data lines and storage elements for selectively generating parity to designate the validity of the selected group of data connected in the portion of storage elements selected by the address lines and storing the parity in the array with the data. Control circuitry is further included for controlling the generation of parity by the parity circuit. The parity generation in this memory system is programmable according to control lines that are connected to the control circuit. The parity circuit may generate the parity output either in the same cycle as the memory access or in the next succeeding cycle of memory access. The output buffer for the parity signal may also be programmable in either a push-pull or a pull-down only configuration.