Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, a direct memory access circuit for transferring data between a buffer established in system memory by an application program and the FIFO buffer circuit, computer implemented software means for establishing a transfer buffer in system memory, circuitry for determining from a command which application program has initiated the command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer circuit at any time.

Abstract: Apparatus and a method by which the flow of DMA-transferable data from an application program to an input/output device using a direct memory access circuit may be halted when the device is unable to respond to DMA-transferable data sent to it. The apparatus includes circuitry for ascertaining whether the input/output device is able to respond to DMA-transferable data transferred to the input/output device, a circuit for storing the DMA-transferable data transferred to the input/output device to which the input/output device is unable to respond, and circuitry for generating a signal to disable immediately the flow of DMA-transferable data to the input/output device and an interrupt to assure that the DMA-transferable data is handled in an expeditious manner.

Abstract: A direct memory access (DMA) arrangement having a DMA circuit which is positioned with an input/output device, the DMA circuit including a first register for storing a reference value pointing to a first data structure established by an application program which includes details of a transfer buffer in memory in which data is stored for transfer to the I/O device, two additional registers for storing an address and a range at which the data is stored within the transfer buffer in memory, and a fourth register for storing a reference value pointing to a second data structure which includes details describing a notification area of memory at which a notification from the DMA circuit that a transfer of data has been completed may be stored.

Abstract: An input circuit for an input/output device adapted for use in a computer system including a first section having a storage circuit holding physical addresses of input/output devices which are translations of selected input/output bus addresses, and a comparator circuit for testing an address in a command from application programs including both data and an address for the data with the recently accessed addresses to obtain a translation from the storage circuit; and a second section including a hash table including translations of physical addresses to be placed in the storage circuit.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit accessed at a physical input/output address for translating addresses and data in commands from applications programs to physical input/output device addresses and for changing the context of an input/output device for which an address translation is furnished.

Abstract: A method of controlling the routing of input/output operations including providing a series of commands expressing connections between sources of data, processing elements, and destinations for data to carry out an input/output operation; compiling a data structure for the input/output operation from the series of commands, the data structure including context defining connections between each of the sources of data, processing elements, and destinations for data; and using the data structure to set connecting context to make connection expressed between each of the sources of data, processing elements, and destinations for data whenever the input/output operation is to be accomplished.

Abstract: An input/output control unit which provides a large amount of input/output address space divisible into areas each of which is a multiple of the system memory management unit page size and thus may be allotted to only one of the individual application programs using a computer system by an input/output device driver. The control unit is able to determine from command addresses provided by the application programs both the application program which is involved in the operation and the address area which has been allotted solely to that application program. This use of these addresses in the input/output address space which have been allotted solely to one application program allows the application programs to write directly to the input/output devices while still maintaining the integrity of the system.

Abstract: A digital system which uses an arrangement of one or more parallel FIFO buffers in which each FIFO buffer handles data from only one application program at any time. In order to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer, each FIFO buffer includes a flow control register which must be read by the processing unit running the application before writing data to an input/output device. The register stores a value which indicates the amount of space available in the FIFO buffer to which data may be written. Reading this register tells the application program how much data may be written without running the risk of overflowing the data storage area which the input/output device has available.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command.

Abstract: A DMA controller which responds without operating system intervention to virtual addresses provided by application programs, and a memory management unit for providing translations between physical addresses of input/output devices and addresses on a system input/output bus for data transferred by the DMA controller.

Abstract: An input circuit for an input/output device adapted for use in a computer system in which a command includes information indicating an application program which initiated the command, the input circuit including a first-in first-out (FIFO) buffer circuit having a plurality of stages, each stage providing storage for commands from application programs including both data and an address for the data, circuitry for determining from a command an application program which has initiated a command, and circuitry for assuring that commands from only one application program reside in the FIFO buffer at any time.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, and additional hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the hardware for translating the input/output address to a physical address space of an input/output device.

Abstract: A computer system including a central processing unit, a system input/output bus, an input/output device, and an input/output control unit joined to the system input/output bus for translating addresses on the system input/output bus to physical input/output device addresses.

Abstract: A system which uses an arrangement of FIFO buffers which include circuitry to assure that no data written to a FIFO buffer by an application program will overflow the FIFO buffer. Each FIFO buffer includes a flow control register which stores a value which indicates the amount of space available in the FIFO to which data may be written. In order to allow for situations in which data is available at a FIFO buffer which cannot be immediately utilized for some reason, an overflow storage area is provided for storing data transferred to the FIFO buffer in excess of the number of stages of the FIFO circuit which are available to store data. The flow control circuitry also includes circuitry for assuring that data which is placed in the overflow storage area is handled in the appropriate sequence.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, and apparatus for handling a failure to provide an address translation.

Abstract: Hardware input/output control apparatus for use in a computer system which control apparatus is joined to a plurality of input/output devices, and includes circuitry which responds to commands from unprivileged application programs addressed to input/output devices joined to the hardware input/output apparatus for selecting a context to be placed on an addressed input/output device to function with an application program sending the command. Context switching is effected in response to commands from unprivileged application programs without involving the operating system or trusted code.

Abstract: A hardware encoding circuit which generates a code value unique to a particular computer, stores a password unique to an application program and to the particular computer, tests the stored password against a verification value generated by the hardware encoding program each time the application program is run, and generates an error signal if the stored password and the verification value do not match.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including a circuit which responds to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address of an input/output device and transferring the command to the physical address of an input/output device, a translation table which responds to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the first hardware means, each selection of a safe translation being accomplished using an arbitrary name originally provided by the unprivileged application program; and a database of data structures which individually include a physical address of an input/output device and can be copied and named by application programs to provide safe translation for storage in the translation t

Abstract: A flow control circuit for a computer system including a first-in first-out buffer including a register for storing a value indicating the number of stages of the FIFO which are available to store data, circuitry for detecting whether an input/output device is able to process data more rapidly than the FIFO is emptied, and circuitry for providing an value greater than the number of stages actually available for storage in the FIFO if the input/output device is able to process data more rapidly than the FIFO is emptied.

Abstract: Hardware input/output address translation apparatus adapted for use in a multitasking computer system including hardware responsive to commands from an unprivileged application program addressed to an input/output address for translating the input/output address to a physical address space of an input/output device and transferring the command to the physical address of an input/output device, and additional hardware responsive to commands from an unprivileged application program addressed to an input/output address for selecting from safe translations of input/output addresses to physical address spaces of input/output devices for the hardware for translating the input/output address to a physical address space of an input/output device.