Abstract: A data processor (100) has a memory operable to store data values; a memory protection unit (130) operable to associate memory attributes with portions of said memory and to identify a plurality of memory regions corresponding to respective address ranges of said memory. The memory protection unit is operable to associate with at least one of the plurality of memory regions (150) a respective memory region specifier comprising an attributes field (230) for defining a set of memory attributes associated with said memory region and a sub-region field (240) for holding a sub-region membership value. The sub-region membership value specifies, for each of a plurality of sub-regions of the memory region, whether respective sub-regions (160-1 to 160-8) are member sub-regions or non-member sub-regions such that said memory attributes are applied to said member sub-regions but are not applied to said non-member sub-regions.

Abstract: A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to data to produce one of the data values for the data processing operation. Further, a plurality of registers are provided for storing data. The instruction has a register specifier field for identifying a register and a shift specifier field for specifying a shift to be applied to that register's data in order to produce one of the data values for the data processing operation.

Abstract: The present invention provides techniques for bit field manipulation, and in particular techniques for bit field extraction and bit field insertion. Data processing apparatus, methods and computer program products are provided. One data processing apparatus comprises data processing logic operable to perform data processing operations on at least one data value; and instruction decode logic operable in response to a bit field extract instruction, which enables a predetermined sequence of bits from the at least one data value to be provided as a sign-extended or zero-extended bit field extracted data value, to control the data processing logic.

Abstract: A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8 for the multiple SIMD data elements to be manipulated by that data processing instruction. A given data processing element may be accessed via different registers depending upon the mapping between the register specifier, the register size and the data element size to a particular location within the register data store 20.

Abstract: The present invention provides a data processing apparatus and method for performing data processing operations on floating point data elements. The data processing apparatus has processing logic for performing data processing operations on the floating point data elements, and decode logic operable to decode a data processing instruction in order to determine a corresponding data processing operation to be performed by the processing logic. The data processing instruction has an m-bit immediate value encoded therein. Further, constant generation logic is provided to perform a logical operation on the m-bit immediate value in order to generate an n-bit floating point constant for use as at least one input floating point data element for the processing logic when performing the corresponding data processing operation. The values “n” and “m” are integers, and n is greater than m. This approach provides a particularly efficient technique for generating floating point constants.

Abstract: A processor core 4 is provided with an interrupt controller 22 which serves to set an interrupt mask bit F and a hardware control when an interrupt fiq occurs. A masking control signal NMI serves to either allow or prevent the software clearing of the interrupt mask bit F.

Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor. (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.

Abstract: Within a SIMD processor 2 data processing instructions are provided which specify parallel lanes of processing to be performed upon respective data elements. The data elements are permitted to vary in size whilst the number of processing lanes remain constant. Thus, the destination register size for a multiplication may be double the source register size.

Abstract: The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to perform a data processing operation on one or more data elements accessed in at least one of the registers. Further, access logic is provided which is operable in response to an access instruction to perform an access operation in order to move a number of data elements between specified registers and a portion of a memory, the portion having a start address specified by the access instruction. Further, the access instruction has an alignment specifier associated therewith which is settable either to a first value or one of a plurality of second values.

Abstract: A water quality monitor receives water that has passed through a water softener treatment tank. The monitor contains a sample of ion exchange resin that is exposed to the water and which shrinks in volume when the water quality deteriorates to the point where it is no longer being softened. Shrinking of the resin sample signals that corrective action should be taken, such as regenerating the softener. Signaling may be a visual or audible signal or it may involve closing a valve preventing the flow of service water to one or more points of use, or restricting the flow to the extent that the restricted flow constitutes a signal to the user. The sample ion exchange resin is contained in a replaceable cartridge that can be inserted into the monitor and replaced after the monitor has functioned to signal deteriorating quality.

Abstract: An improved control for a resin bed water softener includes a microcomputer which is supplied with input data from a flowmeter indicative of the quantity of soft water leaving the softener. In accordance with the flow data, the microcomputer determines the amount of water used since the last regeneration and also determines the average daily soft water consumption. The microcomputer also coupled to a data input device and receives input data indicative of the total resin bed treating capacity and the incoming water hardness. At a prescribed hour each day, the microcomputer determines the remaining water softener resin bed treating capacity as calculated from the water hardness, the total resin bed treating capacity and the amount of water used since the last regeneration.

Abstract: An improved control for a water softener includes a resin bed sensor for sensing when the resin bed has been depleted to a predetermined percentage of the total resin bed treating capacity. The resin bed sensor is connected to a microcomputer which is also coupled to a flow meter to receive data therefrom indicative of the quantity of treated water leaving the water treatment device over a given period of time. When the resin bed sensor signals the microcomputer that the resin bed has been depleted to the predetermined capacity the microcomputer calculates the total softening capacity of the resin bed. Each day, the microcomputer computes both the total quantity of treated water consumed since the last regeneration and the remaining capacity of the resin bed. The microcomputer also maintains a record in memory of the previous 7 days' usage and the average usage is calculated to establish a soft water reserve value.

Abstract: An improved control for a resin bed water softener includes a microcomputer which is supplied with input data from a flowmeter indicative of the quantity of soft water leaving the softener. In accordance with the flow data, the microcomputer determines the amount of water used since the last regeneration and also determines the average daily soft water consumption. The microcomputer also coupled to a data input device and receives input data indicative of the total resin bed treating capacity and the incoming water hardness. At a prescribed hour each day, the microcomputer determines the remaining water softener resin bed treating capacity as calculated from the water hardness, the total resin bed treating capacity and the amount of water used since the last regeneration.