Abstract: A data processing system is described utilizes a multiplier-accumulator 108 that performs both a first class of multiply-accumulate instructions and a second class of multiply-accumulate instructions. The first class of multiply-accumulate instructions are of the form N*N+N.fwdarw.N and the second class of multiply-accumulate instructions are of the form N*N+2N.fwdarw.2N. The second class of multiply-accumulate instructions provide a greater precision of arithmetic in a single instruction and avoid the use of excessive instruction set space by being constrained that the result is written back into the two registers from which the 2N-bit accumulate value was taken. The multiplier-accumulator also provides N*N.fwdarw.N and N*N.fwdarw.2N multiplication operations.

Abstract: A data processing system is described utilising multiple instruction sets. The program instruction words are supplied to a processor core 2 via an instruction pipeline 6. As program instruction words of a second instruction set pass along the instruction pipeline, they are mapped to program instruction words of the first instruction set. The second instruction set has program instruction words of a smaller bit size than those of the first instruction set and is a subset of the first instruction set. Smaller bit size improves code density, whilst the nature of the second instruction set as a subset of the first instruction set enables a one-to-one mapping to be efficiently performed and so avoid the need for a dedicated instruction decoder for the second instruction set.

Abstract: A pipeline processor 2 having an associated branch cache 4 is provided. Each cache line 12 of the branch cache stores a cache TAG, a next branch data value R, a target address value TA and a target instruction value TI. The next branch data value indicates when the next branch instruction will be encountered in the stream of instructions fed to the pipeline processor. This data is used such that following a branch cache hit, no further reading of the branch cache is made until the next branch data indicates that the next branch instruction should have been reached. At this stage, the branch cache 4 is read to see if it contains corresponding data for that next branch instruction that will avoid the need to decode that next branch instruction before instructions from the target address of that branch instruction can be fed into the pipeline. The avoiding of the need to read the branch cache for every instruction fed into the pipeline saves power.