Patents by Inventor David Vincent Caletka

David Vincent Caletka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7703199
    Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Grant
    Filed: May 24, 2006
    Date of Patent: April 27, 2010
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Publication number: 20080119029
    Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
    Type: Application
    Filed: January 17, 2008
    Publication date: May 22, 2008
    Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
  • Patent number: 7348261
    Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
    Type: Grant
    Filed: May 15, 2003
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
  • Patent number: 7086147
    Abstract: Solder balls such as, low melt C4 solder balls, undergo volume expansion during reflow, such as may occur during attachment of chip modules to a PCB. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodated this volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Patent number: 6905961
    Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.
    Type: Grant
    Filed: January 3, 2003
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, William Infantolino, Eric Arthur Johnson
  • Publication number: 20040183094
    Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Application
    Filed: January 29, 2004
    Publication date: September 23, 2004
    Applicant: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Patent number: 6686664
    Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: February 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Publication number: 20030199121
    Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
    Type: Application
    Filed: May 15, 2003
    Publication date: October 23, 2003
    Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
  • Patent number: 6627998
    Abstract: A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: September 30, 2003
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe
  • Patent number: 6595784
    Abstract: An interposer member having strategically positioned apertures for electrically connecting an electronic device to a circuitized substrate. The member includes a homogeneous elastomer core having strategically positioned apertures. The apertures are positioned through the member approximately equidistant between adjacent plated through holes and/or conductive pads. Such positioning relieves stress from the plated through holes and/or conductive pads, and increases the contact compliancy of the member.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: July 22, 2003
    Assignee: International Business Machines Corporation
    Inventors: William Louis Brodsky, David Vincent Caletka
  • Publication number: 20030090000
    Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.
    Type: Application
    Filed: January 3, 2003
    Publication date: May 15, 2003
    Inventors: David Vincent Caletka, Krishna Darbha, William Infantolino, Eric Arthur Johnson
  • Patent number: 6528892
    Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna NMN Darbha, William NMN Infantolino, Eric Arthur Johnson
  • Publication number: 20020180061
    Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.
    Type: Application
    Filed: June 5, 2001
    Publication date: December 5, 2002
    Applicant: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, William Infantolino, Eric Arthur Johnson
  • Publication number: 20020173175
    Abstract: An interposer member having strategically positioned apertures for electrically connecting an electronic device to a circuitized substrate. The member includes a homogeneous elastomer core having strategically positioned apertures. The apertures are positioned through the member approximately equidistant between adjacent plated through holes and/or conductive pads. Such positioning relieves stress from the plated through holes and/or conductive pads, and increases the contact compliancy of the member.
    Type: Application
    Filed: May 15, 2001
    Publication date: November 21, 2002
    Applicant: International Business Machines Corporation
    Inventors: William Louis Brodsky, David Vincent Caletka
  • Publication number: 20020158110
    Abstract: Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.
    Type: Application
    Filed: April 30, 2001
    Publication date: October 31, 2002
    Applicant: International Business Machines Corporation
    Inventors: David Vincent Caletka, Krishna Darbha, Donald W. Henderson, Lawrence P. Lehman, George Henry Thiel
  • Patent number: 6051982
    Abstract: A test apparatus including at least one probe member precisely aligned using two spaced apart means (e.g., thin layers) such that the probe can effectively engage a conductor (e.g., solder ball) on an electronic module (e.g., ball grid array package). A compressible member (e.g., elastomeric body) is used to bias the probe toward the conductor. Various probe cross-sectional configurations are also provided. As taught herein, the probe electrically contacts one of the spaced apart means, also conductive, to thus form a circuit which can extend externally of the apparatus (e.g., for connecting to appropriate testing equipment).
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: April 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: David James Alcoe, David Vincent Caletka
  • Patent number: 5947750
    Abstract: An elastomeric structure including two layers, the first having patterned openings therein and adjacent web members, the second including a patterned array of upstanding projections. The openings and projections may be of cylindrical, rectangular, or other configurations and are oriented in highly dense patterns. The elastomeric is positioned with and attached to a base member having a sidewall substantially as high as the corresponding external side surface of the elastomeric's first layer. The sidewall constrains the elastomeric during compression. The invention thereby substantially prevents lateral expansion of the elastomeric's side surface and lateral deflection of both layers, resulting in a uniform distribution of compressive forces on the upstanding projections.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: September 7, 1999
    Assignee: International Business Machines Corporation
    Inventors: David James Alcoe, William Louis Brodsky, David Vincent Caletka
  • Patent number: 5804984
    Abstract: A test apparatus including at least one probe member precisely aligned using two spaced apart means (e.g., thin dielectric layers having copper thereon) such that the probe can effectively engage a conductor (e.g., solder ball) on an electronic module (e.g., ball grid array package). A compressible member (e.g., elastomeric body) is used to bias the probe toward the conductor. Various probe cross-sectional configurations are also provided.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: September 8, 1998
    Assignee: International Business Machines Corporation
    Inventors: David James Alcoe, David Vincent Caletka